coreboot-gerrit April 2022

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Change in coreboot[master]: soc/amd/sabrina: Allow to specify custom SPL File
by Karthik Ramasubramanian (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63313 to look at the new patch set (#4). Change subject: soc/amd/sabrina: Allow to specify custom SPL File ...................................................................... soc/amd/sabrina: Allow to specify custom SPL File PSP needs SPL file to boot. Introduce the support to add SPL file. Currently Sabrina does not have a specific SPL file. Use Cezanne SPL file as a placeholder. BUG=b:224618411 TEST=Build and boot to OS in Skyrim after adding Sabrina specific SPL file. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 --- M src/soc/amd/sabrina/Kconfig M src/soc/amd/sabrina/Makefile.inc M src/soc/amd/sabrina/fw.cfg 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/63313/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 Gerrit-Change-Number: 63313 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/usb/acpi: acpi_power_res_params: Add use_gpio_for_status
by Raul Rangel (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Tim Van Patten. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63558 ) Change subject: drivers/usb/acpi: acpi_power_res_params: Add use_gpio_for_status ...................................................................... Patch Set 2: (3 comments) File src/acpi/device.c: PS2: Split this into its own commit. https://review.coreboot.org/c/coreboot/+/63558/comment/6d5433a8_6eed6168 PS2, Line 698: ; How about: ``` if (params->use_gpio_for_status) { // ACPI IF (_STA() == ACPI_POWER_RESOURCE_STATUS_ON_OP) RETURN } ``` The _STA method in this case verifies if all the GPIOs are in the On state. If not do the full flow. https://review.coreboot.org/c/coreboot/+/63558/comment/12b8db33_60047528 PS2, Line 705: acpigen_write_gpio_status_check Hrmm I don't think we can just bail since the other GPIOs might be in a different state. -- To view, visit https://review.coreboot.org/c/coreboot/+/63558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69eb5f1ad79f3b2980f43dcf4a36585fca198ec9 Gerrit-Change-Number: 63558 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 15:47:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa: Add gpio lock pins
by Tim Wawrzynczak (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Paul Menzel, Reka Norman, Ivy Jian, Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63568 ) Change subject: mb/google/nissa: Add gpio lock pins ...................................................................... Patch Set 3: (3 comments) File src/mainboard/google/brya/variants/baseboard/nissa/gpio.c: https://review.coreboot.org/c/coreboot/+/63568/comment/1e6629b7_0ab25fef PS3, Line 239: PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), I think we had issues with wake from locked GPIOs (e.g. touchpad) on brya? https://review.coreboot.org/c/coreboot/+/63568/comment/1169eb44_953ecc94 PS3, Line 241: PAD_CFG_GPI_SCI_HIGH_LOCK(GPP_F15, NONE, EDGE_SINGLE, LOCK_CONFIG), same here? https://review.coreboot.org/c/coreboot/+/63568/comment/13c4a67e_65629108 PS3, Line 245: PAD_CFG_GPI_SCI_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), does EC wake via GPIO work? -- To view, visit https://review.coreboot.org/c/coreboot/+/63568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Gerrit-Change-Number: 63568 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 15:16:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63540 ) Change subject: mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt ...................................................................... mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt We don't want to enable the speaker on init. It will be enabled while using GPIO AMP codec in depthcharge. BUG=b:223289882 TEST=boot Nipperkin and Dewatt and then verify the devbeep and gpio values in kernel Signed-off-by: Yu-Hsuan Hsu <yuhsuan(a)google.com> Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63540 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index fff98d2..53ff85b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -82,7 +82,7 @@ /* SD_AUX_RESET_L */ PAD_GPO(GPIO_69, HIGH), /* EN_SPKR */ - PAD_GPO(GPIO_70, HIGH), + PAD_GPO(GPIO_70, LOW), /* GPIO_71 - GPIO_73: Not available */ /* Unused TP49 */ PAD_NC(GPIO_74), -- To view, visit https://review.coreboot.org/c/coreboot/+/63540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a Gerrit-Change-Number: 63540 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Yu-hsuan Hsu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63540 ) Change subject: mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > There is an error "ERROR: Remove Gerrit Change-Id's before submitting upstream" for the build bot. […] there was some jenkins breakage after a checkpatch update, but that's fixed now -- To view, visit https://review.coreboot.org/c/coreboot/+/63540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a Gerrit-Change-Number: 63540 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 15:14:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... soc/intel/alderlake: Add support for UFS controller UFS(Universal Flash Storage) is the next generation storage standard and a SCSI storage technology. It is also a successor of eMMC. Following changes are needed to add support for UFS - 1) Add UFS controller to chipset.cb and keep it off by default 2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62856 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Kangheui Won: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 09dc970..caba2c0 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -118,6 +118,7 @@ device pci 10.7 alias thc1 off end device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end + device pci 12.7 alias ufs off end device pci 13.0 alias gspi3 off end device pci 14.0 alias xhci off chip drivers/usb/acpi diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 58f7579..34e9490 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -642,6 +642,11 @@ if (s_cfg->ScsEmmcEnabled) s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode; #endif + + /* UFS Configuration */ + s_cfg->UfsEnable[0] = 0; /* UFS Controller 0 is fuse disabled */ + s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS); + /* Enable Hybrid storage auto detection */ s_cfg->HybridStorageMode = config->hybrid_storage_mode; } 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 10 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating The patch adds mechanism in the Alder Lake SoC code to control PCH USB2 Phy power gating from brya board variant's devicetree. Please refer Intel doc#723158 for more information. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63293 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 2dae9cd..8ee36f6 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -573,6 +573,13 @@ * Default 0. Set this to 1 in order to disable C state demotion. */ bool disable_c1_state_auto_demotion; + + /* + * Enable or Disable PCH USB2 Phy power gating. + * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. + * Workaround for Intel TA# 723158 to prevent possible display flicker. + */ + bool usb2_phy_sus_pg_disable; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 157bf35..58f7579 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -500,6 +500,8 @@ if (config->tcss_ports[i].enable) s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; } + + s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable; } static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 10 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/i2c/designware/dw_i2c: Remove unnecessary tabs in debug log
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63563 ) Change subject: drivers/i2c/designware/dw_i2c: Remove unnecessary tabs in debug log ...................................................................... drivers/i2c/designware/dw_i2c: Remove unnecessary tabs in debug log Before: [DEBUG] dw_i2c: SoC 400/3000 ns Bus: 400/1000000 ns [DEBUG] dw_i2c: period 334 rise 13 fall 2 tlow 174 thigh 80 spk 7 [DEBUG] dw_i2c: hcnt = 104 lcnt = 202 sda hold = 7 After: [DEBUG] dw_i2c: SoC 400/3000 ns Bus: 400/1000000 ns [DEBUG] dw_i2c: period 334 rise 13 fall 2 tlow 174 thigh 80 spk 7 [DEBUG] dw_i2c: hcnt = 104 lcnt = 202 sda hold = 7 BUG=None TEST=Check that the formatting looks correct, as above. Change-Id: I6703a5d6512cee7848edae27afcfd82eb89bcacb Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63563 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 56f3f27..761fa91 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -570,7 +570,7 @@ printk(DW_I2C_DEBUG, "dw_i2c: SoC %d/%d ns Bus: %d/%d ns\n", soc->freq.ticks, soc->freq.ns, bus->freq.ticks, bus->freq.ns); printk(DW_I2C_DEBUG, -" dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n", + "dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n", period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt, spk_cnt); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6703a5d6512cee7848edae27afcfd82eb89bcacb Gerrit-Change-Number: 63563 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcnt
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63562 ) Change subject: mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcnt ...................................................................... mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcnt Configure lcnt and hcnt directly to give the required frequency, tHIGH and tLOW, instead of using rise and fall times. Aim for a frequency of 390 kHz to make sure it doesn't exceed 400 kHz on different boards. BUG=b:227517802 TEST=Probe the clock line and check that it meets the requirements for frequency, tHIGH and tLOW. Change-Id: I4d4f877c1f0cd9aacd3fa152890b7ef82e059f78 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63562 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb 1 file changed, 20 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index c4c4fb3..dfc0a85 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -74,33 +74,43 @@ .i2c[0] = { .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, .data_hold_time_ns = 50, + .speed_config[0] = { + .scl_lcnt = 157, + .scl_hcnt = 78, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, .data_hold_time_ns = 50, + .speed_config[0] = { + .scl_lcnt = 157, + .scl_hcnt = 78, + } }, .i2c[2] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, .data_hold_time_ns = 50, + .speed_config[0] = { + .scl_lcnt = 157, + .scl_hcnt = 78, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, .data_hold_time_ns = 50, + .speed_config[0] = { + .scl_lcnt = 157, + .scl_hcnt = 78, + } }, .i2c[5] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, .data_hold_time_ns = 50, + .speed_config[0] = { + .scl_lcnt = 157, + .scl_hcnt = 78, + } }, }" 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d4f877c1f0cd9aacd3fa152890b7ef82e059f78 Gerrit-Change-Number: 63562 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Create craask variant
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63256 ) Change subject: mb/google/brya: Create craask variant ...................................................................... mb/google/brya: Create craask variant Create the craask variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:None BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CRAASK Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: Icf03e3f18468d7dd207ab200fa2dcf96afd02f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63256 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/craask/include/variant/ec.h A src/mainboard/google/brya/variants/craask/include/variant/gpio.h A src/mainboard/google/brya/variants/craask/memory/Makefile.inc A src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/craask/overridetree.cb 8 files changed, 47 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1fb90c9..0fafc2f 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -118,6 +118,7 @@ default 0x1 if BOARD_GOOGLE_VOLMAR default 0x1 if BOARD_GOOGLE_BANSHEE default 0x1 if BOARD_GOOGLE_KINOX + default 0x0 if BOARD_GOOGLE_CRAASK config DRIVER_TPM_I2C_ADDR hex @@ -170,6 +171,7 @@ default "Crota" if BOARD_GOOGLE_CROTA default "Moli" if BOARD_GOOGLE_MOLI default "Kinox" if BOARD_GOOGLE_KINOX + default "Craask" if BOARD_GOOGLE_CRAASK config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -197,6 +199,7 @@ default "crota" if BOARD_GOOGLE_CROTA default "moli" if BOARD_GOOGLE_MOLI default "kinox" if BOARD_GOOGLE_KINOX + default "craask" if BOARD_GOOGLE_CRAASK config VBOOT select VBOOT_EARLY_EC_SYNC @@ -227,7 +230,7 @@ choice prompt "Cache as RAM (CAR) setup configuration to use" - default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID + default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK default USE_ADL_ENEM config USE_ADL_ENEM diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index e936ca2..b79fce6 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -192,3 +192,7 @@ config BOARD_GOOGLE_KINOX bool "-> Kinox" select BOARD_GOOGLE_BASEBOARD_BRASK + +config BOARD_GOOGLE_CRAASK + bool "-> Craask" + select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/craask/include/variant/ec.h b/src/mainboard/google/brya/variants/craask/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/craask/include/variant/gpio.h b/src/mainboard/google/brya/variants/craask/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/craask/memory/Makefile.inc b/src/mainboard/google/brya/variants/craask/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/63256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf03e3f18468d7dd207ab200fa2dcf96afd02f8b Gerrit-Change-Number: 63256 Gerrit-PatchSet: 7 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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