coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/nissa: Add gpio lock pins
by Eric Lai (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Reka Norman, Ivy Jian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63568 ) Change subject: mb/google/nissa: Add gpio lock pins ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/baseboard/nissa/gpio.c: https://review.coreboot.org/c/coreboot/+/63568/comment/413876d9_a6e165c6 PS3, Line 241: PAD_CFG_GPI_SCI_HIGH_LOCK(GPP_F15, NONE, EDGE_SINGLE, LOCK_CONFIG), > same here? I will test the wake event after P1 build :p WDYT? I only have MB without any keyparts hehe. -- To view, visit https://review.coreboot.org/c/coreboot/+/63568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Gerrit-Change-Number: 63568 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 00:08:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa: Add gpio lock pins
by Eric Lai (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Reka Norman, Ivy Jian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63568 ) Change subject: mb/google/nissa: Add gpio lock pins ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/baseboard/nissa/gpio.c: https://review.coreboot.org/c/coreboot/+/63568/comment/ae24e192_b5c59be2 PS3, Line 239: PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), > I think we had issues with wake from locked GPIOs (e.g. […] haven't test that. What's the Brya's experiment and solution? remove the lock? -- To view, visit https://review.coreboot.org/c/coreboot/+/63568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Gerrit-Change-Number: 63568 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 23:58:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable Pre Reset CPU Telemetry
by Bora Guvendik (Code Review) 14 Apr '22

14 Apr '22

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63616 ) Change subject: soc/intel/alderlake: Enable Pre Reset CPU Telemetry ...................................................................... soc/intel/alderlake: Enable Pre Reset CPU Telemetry Insert CSE timestamps to coreboot timestamp table. TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ifbea7155a294e0039a5bd1d16588775e90a29ae3 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/63616/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 35fd2f7..c30c6b0 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -111,6 +111,7 @@ select SOC_INTEL_COMMON_RESET select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS -- To view, visit https://review.coreboot.org/c/coreboot/+/63616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbea7155a294e0039a5bd1d16588775e90a29ae3 Gerrit-Change-Number: 63616 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Change the name of macros for 'BHD'
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Paul Menzel, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55411 ) Change subject: amdfwtool: Change the name of macros for 'BHD' ...................................................................... Patch Set 26: (1 comment) Patchset: PS26: for better consistency it would be good to also rename the defines in src/soc/amd/common/psp_verstage/include/psp_verstage.h -- To view, visit https://review.coreboot.org/c/coreboot/+/55411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Gerrit-Change-Number: 55411 Gerrit-PatchSet: 26 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 13 Apr 2022 23:29:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add a flag to record the second gen instead of romsig
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63344 ) Change subject: amdfwtool: Add a flag to record the second gen instead of romsig ...................................................................... amdfwtool: Add a flag to record the second gen instead of romsig This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 38 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 23273e6..646a744 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1373,27 +1373,32 @@ } } -static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, - uint8_t efs_spi_readmode, uint8_t efs_spi_speed, - uint8_t efs_spi_micron_flag) +static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, + embedded_firmware *amd_romsig, uint8_t efs_spi_readmode, + uint8_t efs_spi_speed, uint8_t efs_spi_micron_flag) { if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); return 1; } - switch (soc_id) { - case PLATFORM_STONEYRIDGE: + + /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. + * Leave as 0xffffffff for first gen */ + if (cb_config->second_gen) { + amd_romsig->efs_gen.gen = EFS_SECOND_GEN; + amd_romsig->efs_gen.reserved = 0; + } else { amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; amd_romsig->efs_gen.reserved = ~0; + } + + switch (soc_id) { + case PLATFORM_STONEYRIDGE: amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; break; case PLATFORM_RAVEN: case PLATFORM_PICASSO: - /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. - * Leave as 0xffffffff for first gen */ - amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; - amd_romsig->efs_gen.reserved = ~0; amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1413,8 +1418,6 @@ case PLATFORM_CEZANNE: case PLATFORM_MENDOCINO: case PLATFORM_SABRINA: - amd_romsig->efs_gen.gen = EFS_SECOND_GEN; - amd_romsig->efs_gen.reserved = 0; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1471,6 +1474,25 @@ return false; } +static bool is_second_gen(enum platform platform_type) +{ + switch (platform_type) { + case PLATFORM_STONEYRIDGE: + case PLATFORM_RAVEN: + case PLATFORM_PICASSO: + return false; + case PLATFORM_RENOIR: + case PLATFORM_LUCIENNE: + case PLATFORM_CEZANNE: + case PLATFORM_SABRINA: + return true; + case PLATFORM_UNKNOWN: + default: + fprintf(stderr, "Error: Invalid SOC name.\n\n"); + return false; + } +} + int main(int argc, char **argv) { int c; @@ -1702,6 +1724,8 @@ } } + cb_config.second_gen = is_second_gen(soc_id); + if (needs_ish(soc_id)) cb_config.need_ish = true; @@ -1810,7 +1834,7 @@ amd_romsig->xhci_entry = 0; if (soc_id != PLATFORM_UNKNOWN) { - retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, + retval = set_efs_table(soc_id, &cb_config, amd_romsig, efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag); if (retval) { fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); @@ -1822,7 +1846,7 @@ if (cb_config.need_ish) ctx.address_mode = ADDRESS_MODE_2_REL_TAB; - else if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN) + else if (cb_config.second_gen) ctx.address_mode = ADDRESS_MODE_1_REL_BIOS; else ctx.address_mode = ADDRESS_MODE_0_PHY; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 3af4e94..d2571e5 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -276,6 +276,7 @@ bool load_mp2_fw; bool multi_level; bool s0i3; + bool second_gen; bool have_mb_spl; bool recovery_ab; bool need_ish; -- To view, visit https://review.coreboot.org/c/coreboot/+/63344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Gerrit-Change-Number: 63344 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Add a flag to record the second gen instead of romsig
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Bao Zheng, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63344 ) Change subject: amdfwtool: Add a flag to record the second gen instead of romsig ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Gerrit-Change-Number: 63344 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 13 Apr 2022 23:24:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Wonkyu Kim (Code Review) 14 Apr '22

14 Apr '22

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... intel/common/../systemagent: Enable MCHBAR in bootblock MCHBAR is enabled from romstage but GPMR drvier via IOC(IO Cache) uses MCHBAR in bootblock. So, we need to enable MCHBAR early as possible. TEST=boot to OS in TGL RVP and MTL PSS Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb --- M src/soc/intel/common/block/systemagent/systemagent_early.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63615/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index a77b307..1927ea5 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -20,6 +20,9 @@ { uint32_t reg; uint8_t pciexbar_length; + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + }; /* * The PCIEXBAR is assumed to live in the memory mapped IO space under @@ -53,6 +56,10 @@ * to avoid power on default non-zero value (if any). */ pci_write_config32(SA_DEV_ROOT, TSEG, 0); + + /* Enable MCHBAR */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); } void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/google,intel: Split chromeos.c files
by Julius Werner (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Kyösti Mälkki, Fred Reitberger, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 ) Change subject: [WIP] mb/google,intel: Split chromeos.c files ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: So are you saying you want to split these files just so non-CHROMEOS files don't need to include the vendorcode header? I'm not sure that's really worth scattering all these things about in separate files... The line between vboot and Chrome OS is still pretty hazy here anyway, crossystem is also a part of vboot after all, but all the post-firmware-verification parts of vboot are still pretty tightly coupled to Chrome OS requirements (mostly because there hasn't been much interest from other people to reuse them elsewhere). > At the moment reply on patchset 6 unresolved comment would be most valuable. Sorry, I'm not really familiar with the x86 side of this stuff, let's wait for Tim to respond there. -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 13 Apr 2022 22:27:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86: Add function to set `put_back_original_solution` variable
by 9elements QA (Code Review) 14 Apr '22

14 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63485 ) Change subject: cpu/x86: Add function to set `put_back_original_solution` variable ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100886 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100885 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/100884 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/100883 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/100882 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100881 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/100880 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/100879 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100878 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/100877 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/100876 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/100875 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6b5683b2aa7398a5e141f710394ab772e9775e7 Gerrit-Change-Number: 63485 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 13 Apr 2022 22:21:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Set BT USB to use GPIO for status
by Raul Rangel (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Tim Van Patten. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63559 ) Change subject: mb/google/guybrush: Set BT USB to use GPIO for status ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa Gerrit-Change-Number: 63559 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 22:17:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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