coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brask/variants/moli: add delay time to rtd3-cold
by Raihow Shi (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63544 ) Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63544/comment/c6d877e7_53ea4bdd PS1, Line 9: which will turn : off the eMMC controller (a true D3cold state) during the RTD3 sequence. > The reason is that the rise and fall times of each signal may differ by board, and so those board-sp […] Ok, I modify the commit message, please review it, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/63544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Gerrit-Change-Number: 63544 Gerrit-PatchSet: 9 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 14 Apr 2022 06:08:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: add delay time to rtd3-cold
by Raihow Shi (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, Felix Held. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63544 to look at the new patch set (#9). Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold ...................................................................... mb/google/brask/variants/moli: add delay time to rtd3-cold This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence, the reason is that the rise and fall times of each signal may differ by board, and so those board-specific delays must be taken into account when power sequencing. We checked power on sequence requires enable pin prior to reset pin, so added delay to meet the sequence. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:228907551 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/63544/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/63544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Gerrit-Change-Number: 63544 Gerrit-PatchSet: 9 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm_module_load: Rewrite setup_stub
by Shawn C (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Arthur Heymans. Shawn C has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63478 ) Change subject: cpu/x86/smm_module_load: Rewrite setup_stub ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: Nice hunt, Arthur! The attack surface in coreboot is lesser than UEFI but the misconfig during the setup will lead to serious issue. This one is neat and worth a CVE. Please use CVE-2022-29264 as record. -- To view, visit https://review.coreboot.org/c/coreboot/+/63478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ef9d6a30f3039f25e2cde975086a1365ca4182 Gerrit-Change-Number: 63478 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 14 Apr 2022 05:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable Pre Reset CPU Telemetry
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Bora Guvendik, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63616 ) Change subject: soc/intel/alderlake: Enable Pre Reset CPU Telemetry ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/63616/comment/201474d3_e85a214d PS1, Line 114: select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY > Seems reasonable to leave it here with `if SOC_INTEL_CSE_LITE_SKU` +1 to if suggestion. -- To view, visit https://review.coreboot.org/c/coreboot/+/63616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbea7155a294e0039a5bd1d16588775e90a29ae3 Gerrit-Change-Number: 63616 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Apr 2022 05:30:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: add delay time to rtd3-cold
by Raihow Shi (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63544 ) Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63544/comment/ef839db3_91693dff PS6, Line 12: We checked power on sequence requires enable pin prior to reset pin, : so added delay to meet the sequence. : Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. > nit: remove line break between lines 11 and 12 OR add another line break between them (new paragraph […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Gerrit-Change-Number: 63544 Gerrit-PatchSet: 8 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 14 Apr 2022 05:23:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: add delay time to rtd3-cold
by Raihow Shi (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: YH Lin, Paul Menzel, Zhuohao Lee, Felix Held. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63544 to look at the new patch set (#8). Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold ...................................................................... mb/google/brask/variants/moli: add delay time to rtd3-cold This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin, so added delay to meet the sequence. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:228907551 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/63544/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/63544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Gerrit-Change-Number: 63544 Gerrit-PatchSet: 8 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/vilboz: Add new memory Micron MT40A1G16TB-062E:F
by Frank Wu (Code Review) 14 Apr '22

14 Apr '22

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63621 ) Change subject: mb/google/zork/var/vilboz: Add new memory Micron MT40A1G16TB-062E:F ...................................................................... mb/google/zork/var/vilboz: Add new memory Micron MT40A1G16TB-062E:F Add new ram_id:1101 for memory part MT40A1G16TB-062E:F. BUG=b:b:229036449 BRANCH=firmware-zork-13434.B TEST=FW_NAME=vilboz emerge-zork coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Iae4279b4e1dcbdc1f2b41c88bda412edd8997845 --- M src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc M src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63621/1 diff --git a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc index 7853c15..e09c931 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc @@ -17,3 +17,4 @@ SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 10(0b1010) Parts = MT40A512M16TB-062E:R SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 11(0b1011) Parts = 4JQA-0622AD SPD_SOURCES += spd/ddr4/set-0/spd-9.hex # ID = 12(0b1100) Parts = K4AAG165WB-BCWE +SPD_SOURCES += spd/ddr4/set-0/spd-9.hex # ID = 13(0b1101) Parts = MT40A1G16TB-062E:F diff --git a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt index f3bd888..5fee193 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt @@ -15,3 +15,4 @@ MT40A512M16TB-062E:R 10 (1010) 4JQA-0622AD 11 (1011) K4AAG165WB-BCWE 12 (1100) +MT40A1G16TB-062E:F 13 (1101) diff --git a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt index 9947953..2d14913 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt @@ -18,3 +18,4 @@ MT40A512M16TB-062E:R, 10 4JQA-0622AD, 11 K4AAG165WB-BCWE, 12 +MT40A1G16TB-062E:F, 13 -- To view, visit https://review.coreboot.org/c/coreboot/+/63621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4279b4e1dcbdc1f2b41c88bda412edd8997845 Gerrit-Change-Number: 63621 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: spd/ddr4: Add new SPD Micron MT40A1G16TB-062E:F
by Frank Wu (Code Review) 14 Apr '22

14 Apr '22

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63620 ) Change subject: spd/ddr4: Add new SPD Micron MT40A1G16TB-062E:F ...................................................................... spd/ddr4: Add new SPD Micron MT40A1G16TB-062E:F Add Micron MT40A1G16TB-062E:F in the memory_parts.json and re-generate the SPD ID for it. BUG=b:229036449 BRANCH=firmware-zork-13434.B TEST=FW_NAME=vilboz emerge-zork coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: If7704671994b231c3839efca741fa31446481aa8 --- M spd/ddr4/memory_parts.json M spd/ddr4/set-0/parts_spd_manifest.generated.txt 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/63620/1 diff --git a/spd/ddr4/memory_parts.json b/spd/ddr4/memory_parts.json index 66be6a9..0b6507c 100644 --- a/spd/ddr4/memory_parts.json +++ b/spd/ddr4/memory_parts.json @@ -249,6 +249,17 @@ "packageBusWidth": 16, "ranksPerPackage": 1 } + }, + { + "name": "MT40A1G16TB-062E:F", + "attribs": { + "speedMTps": 3200, + "CL_nRCD_nRP": 22, + "capacityPerDieGb": 16, + "diesPerPackage": 1, + "packageBusWidth": 16, + "ranksPerPackage": 1 + } } ] } diff --git a/spd/ddr4/set-0/parts_spd_manifest.generated.txt b/spd/ddr4/set-0/parts_spd_manifest.generated.txt index fd677b1..dcd7928 100644 --- a/spd/ddr4/set-0/parts_spd_manifest.generated.txt +++ b/spd/ddr4/set-0/parts_spd_manifest.generated.txt @@ -21,3 +21,4 @@ MT40A1G16RC-062E:B,spd-9.hex MT40A512M16TB-062E:R,spd-1.hex 4JQA-0622AD,spd-1.hex +MT40A1G16TB-062E:F,spd-9.hex -- To view, visit https://review.coreboot.org/c/coreboot/+/63620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7704671994b231c3839efca741fa31446481aa8 Gerrit-Change-Number: 63620 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Nick Vaccaro, Eric Lai, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63552 ) Change subject: mb/google/brya: Reset XHCI controller while preparing for S5 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > is this problem specific to google/brya or will it happen on all boards using the same soc? if the latter is the case, this should probably be done in the corresponding soc code's smi sleep handler @Felix, so far we have only seen this issue with ADL-P and ADL-N chrome ref designs and Intel is investigating further to root cause and may be once they provide the TA for this issue, it can re-land into the SOC code. At this moment, don't want to disturb other devices with ADL-SoC unless issue is prove there. WDYT about this approach ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Gerrit-Change-Number: 63552 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 14 Apr 2022 04:21:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Wonkyu Kim, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: may be commit msg need some rework. -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 04:18:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022