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Change subject: soc/intel/fast_spi: Use `need_restore_mtrr()` to clear temp MTRR
......................................................................
Patch Set 2:
(1 comment)
File src/cpu/x86/mtrr/mtrrlib.c:
https://review.coreboot.org/c/coreboot/+/63492/comment/5763e43e_dce8a62a
PS1, Line 52: /* Need to restore mtrr later using remove_temp_solution. */
: if (ENV_RAMSTAGE)
: need_restore_mtrr();
> Ack
@Arthur, can you please take a look into this Temp solution, till we figure out how to manage ramstage Temp MTRR solution in better way using CB:63550 or CB:63555.
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Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold
......................................................................
mb/google/brask/variants/moli: add delay time to rtd3-cold
This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence,
which will turn off the eMMC controller (a true D3cold state)
during the RTD3 sequence.
We checked power on sequence requires enable pin prior to reset pin,
so added delay to meet the sequence.
Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.
BUG=b:228907551
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300
---
M src/mainboard/google/brya/variants/moli/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
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Change subject: mb/google/brask/variants/moli: remove i2c1 in overridetree for moli
......................................................................
mb/google/brask/variants/moli: remove i2c1 in overridetree for moli
remove i2c1 because brask devicetree is already have.
BUG=b:220814038
TEST=emerge-brask coreboot.
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Change subject: mb/google/brya: Add TPM I2C for crota
......................................................................
mb/google/brya: Add TPM I2C for crota
Add TPM I2C for crota to avoid TPM I2C fail.
BUG=b:226315394
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---
M src/mainboard/google/brya/Kconfig
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63617/3
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Change subject: coreboot_tables: Add PCIe info to coreboot table
......................................................................
Patch Set 16:
(1 comment)
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/63251/comment/82e29cfd_13640ba6
PS11, Line 36: CB_ERR
> Yeah, sounds like a good idea to me.
Done
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Change subject: coreboot_tables: Add PCIe info to coreboot table
......................................................................
Patch Set 16:
(1 comment)
Patchset:
PS9:
> So what do we have now -- is this now a MeidaTek-only struct? How likely are we going to be able to […]
Hi Shelley,
Do you think if we can use the same structure here?
For Qualcomm platform, the ATU_BASE is 0x40001000 and the MMIO_BASE is 0x40100000 based on this patch:
https://review.coreboot.org/c/coreboot/+/61773/36/src/soc/qualcomm/sc7280/K…
Is there any chance for Qualcomm to use ctrl_base = 0x40000000, so we can let atu_base = ctrl_base + 0x1000, mmio_base = ctrl_base + 0x100000, what do you think?
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Change subject: soc/intel/alderlake: Enable Pre Reset CPU Telemetry
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/63616/comment/8df1a19f_dd44e864
PS1, Line 114: select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
> Thanks Tim, any preference where it should be? Brya or for ADL?
Seems reasonable to leave it here with `if SOC_INTEL_CSE_LITE_SKU`
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Change subject: mb/google/brya: Add TPM I2C for crota
......................................................................
mb/google/brya: Add TPM I2C for crota
Add TPM I2C for crota to avoid TPM I2C fall.
BUG=b:226315394
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102
---
M src/mainboard/google/brya/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63617/2
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Change subject: mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR
......................................................................
mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on lantis.
BUG=b:223687184
TEST=emerge-dedede coreboot
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace
---
A src/mainboard/google/dedede/variants/lantis/Makefile.inc
A src/mainboard/google/dedede/variants/lantis/ramstage.c
2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/63112/5
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