coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Julius Werner (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Shelley Chen, Taniya Das. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 11 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 21:35:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Sridhar Siricilla, Nick Vaccaro, Eric Lai. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63552 ) Change subject: mb/google/brya: Reset XHCI controller while preparing for S5 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: is this problem specific to google/brya or will it happen on all boards using the same soc? if the latter is the case, this should probably be done in the corresponding soc code's smi sleep handler -- To view, visit https://review.coreboot.org/c/coreboot/+/63552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Gerrit-Change-Number: 63552 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 21:32:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/xhci: Add function to reset the XHCI controller
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63551 ) Change subject: soc/intel/cmn/xhci: Add function to reset the XHCI controller ...................................................................... soc/intel/cmn/xhci: Add function to reset the XHCI controller This patch adds `xhci_host_reset()` to reset XHCI controller and the scope of this function is with SMM hence, compiling xhci.c for SMM as well. Also, refactored `xhci.c` code to keep PCI enumeration within the scope of `ramstage` alone hence, guarded with `ENV_RAMSTAGE` env_variable. BUG=b:227289581 TEST=Able to perform a call from `xhci_host_reset` from S5 smi handler. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/63551 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/common/block/xhci/Makefile.inc M src/soc/intel/common/block/xhci/xhci.c 3 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 1adcbc0..7e2b76e 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -46,6 +46,8 @@ bool xhci_update_wake_event(const struct xhci_wake_info *wake_info, size_t wake_info_count); +/* xhci_host_reset() - Function to reset the host controller */ +void xhci_host_reset(void); void soc_xhci_init(struct device *dev); /* diff --git a/src/soc/intel/common/block/xhci/Makefile.inc b/src/soc/intel/common/block/xhci/Makefile.inc index d1c505e..831992a 100644 --- a/src/soc/intel/common/block/xhci/Makefile.inc +++ b/src/soc/intel/common/block/xhci/Makefile.inc @@ -1,4 +1,5 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI) += xhci.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG) += elog.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI) += xhci.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG) += elog.c diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 9317bb0..a289061 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -13,9 +13,33 @@ #define XHCI_USB2 2 #define XHCI_USB3 3 +#define XHCI_USBCMD 0x80 +#define USBCMD_HCRST (1 << 1) + /* Current Connect Status */ #define XHCI_STATUS_CCS (1 << 0) +static uint8_t *xhci_mem_base(void) +{ + uint32_t mem_base = pci_read_config32(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0); + + /* Check if the controller is disabled or not present */ + if (mem_base == 0 || mem_base == 0xffffffff) + return 0; + + return (uint8_t *)(mem_base & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +void xhci_host_reset(void) +{ + uint8_t *xhci_base = xhci_mem_base(); + if (!xhci_base) + return; + + setbits8(xhci_base + XHCI_USBCMD, USBCMD_HCRST); +} + +#if ENV_RAMSTAGE static bool is_usb_port_connected(const struct xhci_usb_info *info, unsigned int port_type, unsigned int port_id) { @@ -134,3 +158,4 @@ .vendor = PCI_VID_INTEL, .devices = pci_device_ids, }; +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc Gerrit-Change-Number: 63551 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/mtrr: Use `need_restore_mtrr` to set put_back_original_solution
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63491 ) Change subject: cpu/x86/mtrr: Use `need_restore_mtrr` to set put_back_original_solution ...................................................................... cpu/x86/mtrr: Use `need_restore_mtrr` to set put_back_original_solution This patch calls into need_restore_mtrr() from the mtrr_use_temp_range function to set `put_back_original_solution` to discard any temporary MTRR range prior to boot to payload. BUG=b:225766934 TEST=Able to build and boot google/brya to verify that `remove_temp_solution()` is able to discard any temporary MTRR range before booting to payload. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I2e00ec593847e1eb173d5ac77b15b50342860f89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63491 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index e1bdf45..288f06d 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -908,7 +908,7 @@ (long long)begin, (long long)begin + size, (long long)size, type); else - put_back_original_solution = true; + need_restore_mtrr(); memranges_teardown(&addr_space); } 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e00ec593847e1eb173d5ac77b15b50342860f89 Gerrit-Change-Number: 63491 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86: Add function to set `put_back_original_solution` variable
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63485 ) Change subject: cpu/x86: Add function to set `put_back_original_solution` variable ...................................................................... cpu/x86: Add function to set `put_back_original_solution` variable `put_back_original_solution` variable in mtrr.c is static, but there is a need to set put_back_original_solution outside of mtrr.c in order to let `remove_temp_solution` to drop any temporary MTRRs being set outside `mtrr_use_temp_range()`, for example: `set_var_mtrr()` function is used to set MTRRs for the ROM caching. BUG=b:225766934 TEST=Able to build and boot google/redrix. Change-Id: Ic6b5683b2aa7398a5e141f710394ab772e9775e7 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63485 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/x86/mtrr/mtrr.c M src/include/cpu/x86/mtrr.h 2 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 89cac7f..e1bdf45 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -860,6 +860,11 @@ static bool put_back_original_solution; +void need_restore_mtrr(void) +{ + put_back_original_solution = true; +} + void mtrr_use_temp_range(uintptr_t begin, size_t size, int type) { const struct range_entry *r; diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index b8d1517..5a23784 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -96,6 +96,7 @@ /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); void x86_mtrr_check(void); +void need_restore_mtrr(void); /* Insert a temporary MTRR range for the duration of coreboot's runtime. * This function needs to be called after the first MTRR solution is derived. */ 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6b5683b2aa7398a5e141f710394ab772e9775e7 Gerrit-Change-Number: 63485 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: probe privacy screen device by fw_c...
by Felix Held (Code Review) 13 Apr '22

13 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63575 ) Change subject: mb/google/guybrush/var/nipperkin: probe privacy screen device by fw_config ...................................................................... mb/google/guybrush/var/nipperkin: probe privacy screen device by fw_config BUG=b:228448327 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage check ACPI device "LCD" in SSDT Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: I42c5abdbe3bfab72016d56399278a7aff9e33377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63575 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 6d6285a..85581d2 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -188,7 +188,9 @@ register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_18)" - device generic 0.0 on end + device generic 0.0 on + probe KB_MAP KB_MAP_PRIVACY + end end end device ref acp on -- To view, visit https://review.coreboot.org/c/coreboot/+/63575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42c5abdbe3bfab72016d56399278a7aff9e33377 Gerrit-Change-Number: 63575 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/qualcomm/common: Fix mem_chip_info bugs in QcLib glue
by 9elements QA (Code Review) 13 Apr '22

13 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63026 ) Change subject: soc/qualcomm/common: Fix mem_chip_info bugs in QcLib glue ...................................................................... Patch Set 13: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100860 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100859 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/100858 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/100857 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/100856 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100855 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/100854 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/100853 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100852 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/100851 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/100850 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/100849 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281 Gerrit-Change-Number: 63026 Gerrit-PatchSet: 13 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 13 Apr 2022 21:10:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Julius Werner (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Rex-BC Chen, Arthur Heymans, Yu-Ping Wu, Jianjun Wang. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot_tables: Add PCIe info to coreboot table ...................................................................... Patch Set 16: (1 comment) Patchset: PS9: > Since we are only use the 'ctrl_base' field, I removed this structure and only keeps the 'pcie_ctrl_ […] So what do we have now -- is this now a MeidaTek-only struct? How likely are we going to be able to reuse this on other platforms? (I believe +Shelley is working on PCIe support for Qualcomm SoCs, do we need something like this there as well? And would this struct be compatible?) I think if this is going to be called lb_pcie and be integrated directly into the main coreboot-table code, there should be at least a good chance that it will work for other SoCs as well. If we think it's probably just MediaTek specific it should be lb_pcie_mtk or something like that, and it should probably be hooked up through lb_board() or something like that. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 16 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 20:57:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi/device: Early return in _ON if device already enabled
by Raul Rangel (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Tim Van Patten. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63613 ) Change subject: src/acpi/device: Early return in _ON if device already enabled ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/acpi/device.c: https://review.coreboot.org/c/coreboot/+/63613/comment/c9cca681_ddbd9297 PS3, Line 681: (( > There are 2 `((` in the generated ACPI code: […] Interesting... Ok. -- To view, visit https://review.coreboot.org/c/coreboot/+/63613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13aa41766555953b86eded4c72e3b317fe6db5c8 Gerrit-Change-Number: 63613 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 20:47:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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Change in qc_blobs[master]: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes
by Julius Werner (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Shelley Chen, Saurabh Gorecha, Ravi Kumar Bokka, mturney mturney. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/63614 ) Change subject: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes ...................................................................... Patch Set 3: Verified+1 (1 comment) Patchset: PS2: > Julius can you help V+1? You should ask Martin or Patrick to give you those rights. -- To view, visit https://review.coreboot.org/c/qc_blobs/+/63614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I6c60c3642b272fbc57c90ad857044bf69b01fef0 Gerrit-Change-Number: 63614 Gerrit-PatchSet: 3 Gerrit-Owner: Saurabh Gorecha <quic_sgorecha(a)quicinc.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Saurabh Gorecha <quic_sgorecha(a)quicinc.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Wed, 13 Apr 2022 20:46:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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