coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63627 ) Change subject: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration ...................................................................... soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration This patch performs additional SPI lock configuration as per Intel Flash Security Specification. BUG=b:211954778 TEST=Able to build google/brya and verified all flash security recommendations are being met. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 --- M src/soc/intel/common/pch/lockdown/lockdown.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/63627/1 diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 5ab0611..fb7af1c 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> +#include <console/console.h> #include <intelblocks/cfg.h> #include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> @@ -57,9 +58,19 @@ /* Discrete Lock Flash PR registers */ fast_spi_pr_dlock(); + /* Check if SPI transaction is pending */ + if (fast_spi_cycle_in_progress() < 0) + die("SPI Cycle Pending!"); + + /* Clear any outstanding status like AEL, FCERR, FDONE, SAF etc. */ + fast_spi_clear_outstanding_status(); + /* Lock FAST_SPIBAR */ fast_spi_lock_bar(); + /* Set Vendor Component Lock (VCL) */ + fast_spi_vscc0_lock(); + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { /* BIOS Interface Lock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 Gerrit-Change-Number: 63627 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to set SPI controller VCL
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63626 ) Change subject: soc/intel/cmn/fast_spi: Add API to set SPI controller VCL ...................................................................... soc/intel/cmn/fast_spi: Add API to set SPI controller VCL This patch creates a helper function to set SPI controller VCL bit as recommended by Intel Flash Security Specification. BUG=b:211954778 TEST=Able to build google/brya and verified that SPI flash controller MMIO register 0xC4 bit 30 is set. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie9a12db1bab81779fd8e7db90221d08da3c65011 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/63626/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 4ff1e9b..7e8a1a2 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -171,6 +171,23 @@ } /* + * Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30). + */ +void fast_spi_vscc0_lock(void) +{ + void *spibar = fast_spi_get_bar(); + + /* + * SPI Flash Programming Guide Section 5.5.2 describes Vendor Component Lock (VCL). + * It is recommended to set the VCL bit. VCL applies to both VSCC0 and VSCC1. + * Without this bit being set, it is possible to modify Host/GbE VSCC register(s), + * which might results in undesired host and integrated GbE Serial Flash + * functionality. + */ + setbits32(spibar + SPIBAR_SFDP0_VSCC0, SPIBAR_VSCC0_VCL); +} + +/* * Set FAST_SPIBAR Soft Reset Data Register value. */ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index f28865d..1e8bdb3 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -131,6 +131,13 @@ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +/* + * Register Offsets of BIOS Vendor Specific Component Capabilities for + * Component 0 Registers + */ +#define SPIBAR_SFDP0_VSCC0 0xc4 +#define SPIBAR_VSCC0_VCL (1 << 30) + /* Bit definitions for PTINX (0xcc) register */ #define SPIBAR_PTINX_COMP_0 (0 << 14) #define SPIBAR_PTINX_COMP_1 (1 << 14) diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 8c5067d..dbdc666 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -43,6 +43,10 @@ */ void fast_spi_pr_dlock(void); /* + * Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30). + */ +void fast_spi_vscc0_lock(void); +/* * Set FAST_SPIBAR Soft Reset Data Register value. */ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/63626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a12db1bab81779fd8e7db90221d08da3c65011 Gerrit-Change-Number: 63626 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63625 ) Change subject: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status ...................................................................... soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status This patch creates a helper function to clear HSFSTS_CTL (offset 0x04) register Bits 0 to 4. As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation, it's important to clear all SPI outstanding status before setting SPI lock bits. BUG=b:211954778 TEST=Able to build google/brya with this patch and clear SPI controller HSFSTS_CTL register Bits 0 to 4. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/63625/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5a76df3..4ff1e9b 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -428,3 +428,11 @@ bios_cntl |= SPI_BIOS_CONTROL_WPD; pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl); } + +void fast_spi_clear_outstanding_status(void) +{ + void *spibar = fast_spi_get_bar(); + + /* Make sure all W1C status bits get cleared. */ + write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS); +} diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index eb3f2aa..8c5067d 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -5,6 +5,8 @@ #include <types.h> +/* Clear any SPI outstanding status, i.e., FCERR, FDONE etc. */ +void fast_spi_clear_outstanding_status(void); /* Check if SPI transaction is pending */ int fast_spi_cycle_in_progress(void); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/63625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7 Gerrit-Change-Number: 63625 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63624 ) Change subject: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress ...................................................................... soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress This patch creates a helper function to check if any SPI transaction is pending. As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation, it's important to ensure there is no pending SPI transaction before setting SPI lock bits. BUG=b:211954778 TEST=Able to build google/brya with this patch and no error msg seen due to `SPI transaction is pending`. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 --- M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63624/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 269db63..155bc9e 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -161,6 +161,17 @@ return wait_for_hwseq_xfer(ctx, flash_addr); } +int fast_spi_cycle_in_progress(void) +{ + BOILERPLATE_CREATE_CTX(ctx); + + enum errors ret = wait_for_hwseq_spi_cycle_complete(ctx); + if (ret != SUCCESS) + printk(BIOS_ERR, "SPI transaction is pending\n"); + + return ret; +} + /* * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and * that the operation does not cross page boundary. diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index a903ea83..eb3f2aa 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -5,6 +5,8 @@ #include <types.h> +/* Check if SPI transaction is pending */ +int fast_spi_cycle_in_progress(void); /* * Disable the BIOS write protect and Enable Prefetching and Caching. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 Gerrit-Change-Number: 63624 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Use tab instead space
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63623 ) Change subject: soc/intel/cmn/fast_spi: Use tab instead space ...................................................................... soc/intel/cmn/fast_spi: Use tab instead space This patch converts whitespace into tabs to maintain the uniformity across the fast_spi_def.h file. BUG=b:211954778 TEST=Able to build google/brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I56bcd263c6a5c0036e459926a25538e3448fbce6 --- M src/soc/intel/common/block/fast_spi/fast_spi_def.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/63623/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 353c89f..f28865d 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -140,9 +140,9 @@ #define SPIBAR_PTINX_IDX_MASK 0xffc /* Register Offsets of BIOS Flash Program Registers */ -#define SPIBAR_RESET_LOCK 0xf0 -#define SPIBAR_RESET_CTRL 0xf4 -#define SPIBAR_RESET_DATA 0xf8 +#define SPIBAR_RESET_LOCK 0xf0 +#define SPIBAR_RESET_CTRL 0xf4 +#define SPIBAR_RESET_DATA 0xf8 /* Programmable values of Bit0 (SSL) of Set STRAP MSG LOCK (0xF0) Register */ #define SPIBAR_RESET_LOCK_DISABLE 0 /* Set_Strap Lock(SSL) Bit 0 = 0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bcd263c6a5c0036e459926a25538e3448fbce6 Gerrit-Change-Number: 63623 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Implement IOC driver
by Wonkyu Kim (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63198 ) Change subject: soc/intel/common: Implement IOC driver ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63198/comment/2a7b7f3e_54083899 PS12, Line 28: dmi_lockdown_cfg > Do we still need this? I think we don't need this anymore. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Gerrit-Change-Number: 63198 Gerrit-PatchSet: 17 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 06:44:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Wonkyu Kim (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Subrata Banik, Angel Pons. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > may be commit msg need some rework. Commit message are updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 06:43:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Wonkyu Kim (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Wonkyu Kim, Angel Pons. Hello build bot (Jenkins), Subrata Banik, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63615 to look at the new patch set (#3). Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... intel/common/../systemagent: Enable MCHBAR in bootblock MCHBAR is enabled from romstage so far while new SOC like Meteorlake uses MCHBAR in GPMR driver from bootblock. As there is no harm to enable MCHBAR from bootblock even in existing plaforms, enabling it from bootblock in common code. TEST=boot to OS in TGL RVP and MTL PSS Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb --- M src/soc/intel/common/block/systemagent/systemagent_early.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63615/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/banshee: add the smbus addr for dimm1
by Eric Lai (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Frank Wu, John Su, YH Lin, Dtrain Hsu, Ian Feng, Tim Wawrzynczak, Nick Vaccaro, Amanda Hwang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63622 ) Change subject: mb/google/brya/var/banshee: add the smbus addr for dimm1 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Please elaborate why MRC training again. IIUC, banshee only have 2 MC. -- To view, visit https://review.coreboot.org/c/coreboot/+/63622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I708d6c3f7976891b1178e43449168090e215d122 Gerrit-Change-Number: 63622 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 06:39:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: add the smbus addr for dimm1
by Frank Wu (Code Review) 14 Apr '22

14 Apr '22

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63622 ) Change subject: mb/google/brya/var/banshee: add the smbus addr for dimm1 ...................................................................... mb/google/brya/var/banshee: add the smbus addr for dimm1 Align the setting with the adlrvp. BUG=b:213964936 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The MRC training does not be performed again after rebooting. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I708d6c3f7976891b1178e43449168090e215d122 --- M src/mainboard/google/brya/variants/banshee/memory.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/63622/1 diff --git a/src/mainboard/google/brya/variants/banshee/memory.c b/src/mainboard/google/brya/variants/banshee/memory.c index 7371f57..deccf13 100644 --- a/src/mainboard/google/brya/variants/banshee/memory.c +++ b/src/mainboard/google/brya/variants/banshee/memory.c @@ -33,5 +33,7 @@ { spd_info->topo = MEM_TOPO_DIMM_MODULE; spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x51; spd_info->smbus[1].addr_dimm[0] = 0x52; + spd_info->smbus[1].addr_dimm[1] = 0x53; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I708d6c3f7976891b1178e43449168090e215d122 Gerrit-Change-Number: 63622 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2022