coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: soc/intel/mp_init.c: Ensure proper romcache programming
by Arthur Heymans (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Arthur Heymans. Arthur Heymans has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63554 ) Change subject: soc/intel/mp_init.c: Ensure proper romcache programming ...................................................................... soc/intel/mp_init.c: Ensure proper romcache programming AP threads share MTRRs so to avoid APs overwriting the romcache MTRR programming make sure the APs finished. Change-Id: I74892100c19b46729ed401b4a50638d8cf07ece8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/63554/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74892100c19b46729ed401b4a50638d8cf07ece8 Gerrit-Change-Number: 63554 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Arthur Heymans (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Arthur Heymans, Tim Wawrzynczak, Kane Chen. Arthur Heymans has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63553 ) Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus This functions makes sure that all APs finish executing their call before continuing to execute code on the BSP. Change-Id: I70244557bb384739e3bd06de3d8414ec9f4d5f62 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c M src/include/cpu/x86/mp.h 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/63553/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70244557bb384739e3bd06de3d8414ec9f4d5f62 Gerrit-Change-Number: 63553 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges
by Arthur Heymans (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63555 to look at the new patch set (#4). Change subject: cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges ...................................................................... cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges Temporary MTRR setup usually covers the memory mapped flash. On recent Intel hardware the mapping is not coherent. It uses an external window for parts of the BIOS region that exceed 16M. This now allows up to 10 temporary memory ranges. Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/63555/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges
by Arthur Heymans (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63555 ) Change subject: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63555/comment/43782629_1e3d0970 PS2, Line 7: .c > Not needed in prefix. Done https://review.coreboot.org/c/coreboot/+/63555/comment/25857924_aff318dd PS2, Line 9: cover > covers? Done File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/63555/comment/5f4497e6_98ccb600 PS2, Line 912: memranges_teardown(&addr_space); > this can't be happening either... Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Apr 2022 07:27:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib: Treat dimm addr_map 0 as not exist
by Eric Lai (Code Review) 14 Apr '22

14 Apr '22

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63628 ) Change subject: lib: Treat dimm addr_map 0 as not exist ...................................................................... lib: Treat dimm addr_map 0 as not exist Treat dimm addr_map 0 as not exist. addr_map default is 0, we don't set it if there no HW exist. BUG=b:213964936 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The MRC training does not be performed again after rebooting. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac --- M src/lib/spd_cache.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/63628/1 diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c index 44830a8..3814e3c 100644 --- a/src/lib/spd_cache.c +++ b/src/lib/spd_cache.c @@ -155,6 +155,10 @@ bool dimm_changed = false; /* Check if the dimm is the same with last system boot. */ for (i = 0; i < SC_SPD_NUMS && !dimm_changed; i++) { + if (blk->addr_map[i] == 0) { + printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is not exist\n", i); + continue; + } /* Return true if any error happened here. */ if (get_spd_sn(blk->addr_map[i], &sn) == CB_ERR) return true; -- To view, visit https://review.coreboot.org/c/coreboot/+/63628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Gerrit-Change-Number: 63628 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges
by Arthur Heymans (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63555 to look at the new patch set (#3). Change subject: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges ...................................................................... cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges Temporary MTRR setup usually cover the memory mapped flash. On recent Intel hardware the mapping is not coherent. It uses an external window for parts of the BIOS region that exceed 16M. Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/63555/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63624 ) Change subject: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/63624/comment/8ae4d716_faf1a6e4 PS1, Line 168: enum errors > > All across the file 'int' is used for ret (which is the return type of the function as well). […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 Gerrit-Change-Number: 63624 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 07:24:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress
by Werner Zeh (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63624 ) Change subject: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/63624/comment/9703abf1_92ea223a PS1, Line 170: SPI transaction is pending\n Maybe it is worth to make it clear here that the timeout has already elapsed? -- To view, visit https://review.coreboot.org/c/coreboot/+/63624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 Gerrit-Change-Number: 63624 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 07:24:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63624 ) Change subject: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/63624/comment/3986d0fe_3ffd4b3f PS1, Line 168: enum errors > All across the file 'int' is used for ret (which is the return type of the function as well). Why do you switch to 'enum errors' here? > If there is a valid value for that the I guess we could do that consistent in the whole file in a follow-up? valid point. -- To view, visit https://review.coreboot.org/c/coreboot/+/63624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 Gerrit-Change-Number: 63624 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 07:24:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63624 to look at the new patch set (#2). Change subject: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress ...................................................................... soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress This patch creates a helper function to check if any SPI transaction is pending. As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation, it's important to ensure there is no pending SPI transaction before setting SPI lock bits. BUG=b:211954778 TEST=Able to build google/brya with this patch and no error msg seen due to `SPI transaction is pending`. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 --- M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63624/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 Gerrit-Change-Number: 63624 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022