coreboot-gerrit April 2022

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Change in coreboot[master]: Documentation: Add list of boards maintained on each branch
by Martin L Roth (Code Review) 23 Apr '22

23 Apr '22

Attention is currently required from: Arthur Heymans. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63797 ) Change subject: Documentation: Add list of boards maintained on each branch ...................................................................... Patch Set 1: (1 comment) File Documentation/releases/boards_supported_on_branches.md: https://review.coreboot.org/c/coreboot/+/63797/comment/ea979150_7f26646a PS1, Line 265: > Stupid editor. […] Today I learned. In markdown, two or more spaces at the end of a line are used to signify a line break. These were deliberately kept by the editor thinking that they were intentional. -- To view, visit https://review.coreboot.org/c/coreboot/+/63797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee25db13e2c1b0b9131fd2032a26ece45aba4f42 Gerrit-Change-Number: 63797 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 23 Apr 2022 19:32:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <martinroth(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add list of boards maintained on each branch
by Martin L Roth (Code Review) 23 Apr '22

23 Apr '22

Attention is currently required from: Arthur Heymans. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63797 ) Change subject: Documentation: Add list of boards maintained on each branch ...................................................................... Patch Set 1: (4 comments) Patchset: PS1: Since I've gotten positive feedback about this patch, I'll split it into a patch for the script, and another for the documentation. Thanks for the comments here and on the mailing list. File Documentation/releases/boards_supported_on_branches.md: https://review.coreboot.org/c/coreboot/+/63797/comment/6f6fc769_9c28d581 PS1, Line 99: PARALLEL_INIT > AMD_AMDFAM10 Thanks, that should have been removed. https://review.coreboot.org/c/coreboot/+/63797/comment/e763e167_7220788c PS1, Line 109: lenovo/z61t > This one is a variant now. Great, I wasn't completely sure about all of these. https://review.coreboot.org/c/coreboot/+/63797/comment/94f76dfa_ea66015f PS1, Line 265: > spaces Stupid editor. :) -- To view, visit https://review.coreboot.org/c/coreboot/+/63797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee25db13e2c1b0b9131fd2032a26ece45aba4f42 Gerrit-Change-Number: 63797 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 23 Apr 2022 18:18:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function
by Subrata Banik (Code Review) 23 Apr '22

23 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63737 ) Change subject: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function ...................................................................... soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. BUG=b:211954778 TEST=Able to build google/redrix with these changes and boot to OS. > localhost ~ # iotools mmio_read32 0xfe0018c4 0x85000000 (bit 31 is set) > localhost ~ # iotools mmio_read32 0xfe001024 0x00062610 (bits 4, 17 and 18 are set) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63737 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/lockdown.c 1 file changed, 5 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index e9e4b59..b0da51f 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -12,51 +12,17 @@ #include <soc/pm.h> #include <stdint.h> -static void pmc_lock_pmsync(void) -{ - uint8_t *pmcbase; - uint32_t pmsyncreg; - - pmcbase = pmc_mmio_regs(); - - pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); - pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; - write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); -} - -static void pmc_lock_abase(void) -{ - uint8_t *pmcbase; - uint32_t reg32; - - pmcbase = pmc_mmio_regs(); - - reg32 = read32(pmcbase + GEN_PMCON_B); - reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); - write32(pmcbase + GEN_PMCON_B, reg32); -} - -static void pmc_lock_smi(void) -{ - uint8_t *pmcbase; - uint8_t reg8; - - pmcbase = pmc_mmio_regs(); - - reg8 = read8(pmcbase + GEN_PMCON_B); - reg8 |= SMI_LOCK; - write8(pmcbase + GEN_PMCON_B, reg8); -} - static void pmc_lockdown_cfg(int chipset_lockdown) { + uint8_t *pmcbase = pmc_mmio_regs(); + /* PMSYNC */ - pmc_lock_pmsync(); + setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK); /* Lock down ABASE and sleep stretching policy */ - pmc_lock_abase(); + setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) - pmc_lock_smi(); + setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK); } void soc_lockdown_config(int chipset_lockdown) -- To view, visit https://review.coreboot.org/c/coreboot/+/63737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Gerrit-Change-Number: 63737 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/smbus: Add `finalize` operation for smbus
by Subrata Banik (Code Review) 23 Apr '22

23 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63640 ) Change subject: soc/intel/common/smbus: Add `finalize` operation for smbus ...................................................................... soc/intel/common/smbus: Add `finalize` operation for smbus This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs i.e. Post PCI Enumeration. The smbus `.final` operation ensures locking the TCO register when coreboot decides to skip FspNotifyApi() calls. BUG=b:211954778 TEST=Able to build google/brya with these changes and coreboot log with this code change as below with ADL SoC skip calling into FspNotifyAPIs: [INFO ] Finalize devices... [DEBUG] PCI: 00:1f.4 final > localhost ~ # lspci -xxx | less 00:1f.4 Intel Corporation Alder Lake PCH-P SMBus Host Controller (rev 01) Offset 8, Bit 12 a.k.a TCO Lock bit is set (meaning locked). Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie945680049514e6c5d797790a381a6946e836926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63640 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/common/block/smbus/smbus.c 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index d1b6523..7fdbffc 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -7,6 +7,7 @@ #include <device/pci_ids.h> #include <soc/smbus.h> #include <device/smbus_host.h> +#include <intelblocks/tco.h> #include "smbuslib.h" static int lsmbus_read_byte(struct device *dev, u8 address) @@ -63,6 +64,19 @@ IORESOURCE_STORED | IORESOURCE_ASSIGNED; } +/* + * `finalize_smbus` function is native implementation of equivalent events + * performed by each FSP NotifyPhase() API invocations. + * + * Operations are: + * 1. TCO Lock. + */ +static void finalize_smbus(struct device *dev) +{ + if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + tco_lockdown(); +} + static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, @@ -71,6 +85,7 @@ .init = pch_smbus_init, .ops_pci = &pci_dev_ops_pci, .ops_smbus_bus = &lops_smbus_bus, + .final = finalize_smbus, }; static const unsigned short pci_device_ids[] = { 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie945680049514e6c5d797790a381a6946e836926 Gerrit-Change-Number: 63640 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration
by Subrata Banik (Code Review) 23 Apr '22

23 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63631 ) Change subject: soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration ...................................................................... soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration This patch drops SoC specific lpc lock down configuration as commit 63630 (soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration) implements the lpc registers lock down configuration in common code. BUG=b:211954778 TEST=Build. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I99ec6d63dfe9a8ac8d9846067a9afc3ef83dc1c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63631 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/intel/skylake/lockdown.c M src/soc/intel/xeon_sp/lockdown.c 2 files changed, 0 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 2fa53c9..1dd4e56 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -2,20 +2,10 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> -#include <intelblocks/lpc_lib.h> #include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> #include <soc/pm.h> -static void lpc_lockdown_config(int chipset_lockdown) -{ - /* Set BIOS Interface Lock, BIOS Lock */ - if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - lpc_set_bios_interface_lock_down(); - lpc_set_lock_enable(); - } -} - static void pmc_lockdown_config(void) { uint8_t *pmcbase; @@ -33,9 +23,6 @@ void soc_lockdown_config(int chipset_lockdown) { - /* LPC lock down configuration */ - lpc_lockdown_config(chipset_lockdown); - /* PMC lock down configuration */ pmc_lockdown_config(); } diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 0f032fc..49f3f5a 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -3,21 +3,11 @@ #include <device/mmio.h> #include <device/pci.h> #include <intelblocks/cfg.h> -#include <intelblocks/lpc_lib.h> #include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> #include <soc/pci_devs.h> #include <soc/pm.h> -static void lpc_lockdown_config(int chipset_lockdown) -{ - /* Set BIOS Interface Lock, BIOS Lock */ - if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - lpc_set_bios_interface_lock_down(); - lpc_set_lock_enable(); - } -} - static void pmc_lockdown_config(int chipset_lockdown) { uint8_t *pmcbase; @@ -46,7 +36,6 @@ void soc_lockdown_config(int chipset_lockdown) { - lpc_lockdown_config(chipset_lockdown); pmc_lockdown_config(chipset_lockdown); sata_lockdown_config(chipset_lockdown); } 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99ec6d63dfe9a8ac8d9846067a9afc3ef83dc1c2 Gerrit-Change-Number: 63631 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
by Subrata Banik (Code Review) 23 Apr '22

23 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63630 ) Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration ...................................................................... soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration This patch implements a helper function to perform LPC registers lock down configuration. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified LPC PCI configuration register offset 0xDC bits BILD and LE are set. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63630 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/pch/lockdown/lockdown.c 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 8032b4a..cd8b402 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -3,6 +3,7 @@ #include <bootstate.h> #include <intelblocks/cfg.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelpch/lockdown.h> #include <intelblocks/gpmr.h> @@ -88,6 +89,24 @@ } } +static void lpc_lockdown_config(int chipset_lockdown) +{ + /* Set BIOS Interface Lock, BIOS Lock */ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + /* BIOS Interface Lock */ + lpc_set_bios_interface_lock_down(); + + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP)) { + lpc_set_eiss(); + lpc_enable_wp(); + } + + /* BIOS Lock */ + lpc_set_lock_enable(); + } +} + /* * platform_lockdown_config has 2 major part. * 1. Common SoC lockdown configuration. @@ -102,6 +121,9 @@ /* SPI lock down configuration */ fast_spi_lockdown_cfg(chipset_lockdown); + /* LPC/eSPI lock down configuration */ + lpc_lockdown_config(chipset_lockdown); + /* DMI lock down configuration */ lockdown_cfg(); 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Gerrit-Change-Number: 63630 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
by Subrata Banik (Code Review) 23 Apr '22

23 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63777 ) Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg ...................................................................... soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg Typically, the SPIBAR_HSFSTS_W1C_BITS macro is used to clear all HSFSTS register bit-fields with the W1C attribute. So far SPIBAR_HSFSTS_W1C_BITS is 1 byte width hence, missed to clear SAF_CE (bit 8). This patch expands the `SPIBAR_HSFSTS_W1C_BITS` macro to include SAF_CE (bit 8). BUG=b:211954778 TEST=Able to build google/brya with this patch and clear SPI controller HSFSTS_CTL register Bits 0 to 4 and 8. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63777 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/common/block/fast_spi/fast_spi_def.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 0be3dcd..4012c29 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -75,7 +75,7 @@ #define SPIBAR_HSFSTS_AEL (1 << 2) #define SPIBAR_HSFSTS_FCERR (1 << 1) #define SPIBAR_HSFSTS_FDONE (1 << 0) -#define SPIBAR_HSFSTS_W1C_BITS 0xff +#define SPIBAR_HSFSTS_W1C_BITS 0x1ff /* Bit definitions for FADDR (0x08) register */ #define SPIBAR_FADDR_MASK 0x7ffffff -- To view, visit https://review.coreboot.org/c/coreboot/+/63777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 Gerrit-Change-Number: 63777 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [only for test] test gcc-12 snapshot
by Elyes Haouas (Code Review) 23 Apr '22

23 Apr '22

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61533 to look at the new patch set (#5). Change subject: [only for test] test gcc-12 snapshot ...................................................................... [only for test] test gcc-12 snapshot Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.inc M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-11.2.0_gnat.patch R util/crossgcc/patches/gcc-12-20220417_ada-musl_workaround.patch R util/crossgcc/patches/gcc-12-20220417_asan_shadow_offset_callback.patch A util/crossgcc/patches/gcc-12-20220417_gnat.patch R util/crossgcc/patches/gcc-12-20220417_libcpp.patch R util/crossgcc/patches/gcc-12-20220417_libgcc.patch D util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-12-20220417.tar.xz.cksum 10 files changed, 33 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61533/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Gerrit-Change-Number: 61533 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [only for test] test gcc-12 snapshot
by Elyes Haouas (Code Review) 23 Apr '22

23 Apr '22

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61533 to look at the new patch set (#4). Change subject: [only for test] test gcc-12 snapshot ...................................................................... [only for test] test gcc-12 snapshot Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.inc M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-11.2.0_gnat.patch R util/crossgcc/patches/gcc-12-20220417_ada-musl_workaround.patch R util/crossgcc/patches/gcc-12-20220417_asan_shadow_offset_callback.patch A util/crossgcc/patches/gcc-12-20220417_gnat.patch R util/crossgcc/patches/gcc-12-20220417_libcpp.patch R util/crossgcc/patches/gcc-12-20220417_libgcc.patch D util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-12-20220417.tar.xz.cksum 10 files changed, 30 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61533/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Gerrit-Change-Number: 61533 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/*: Set SMM SMRR code access check bit
by Subrata Banik (Code Review) 23 Apr '22

23 Apr '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Tim Wawrzynczak, Suresh Bellampalli, Paul Menzel, Vanessa Eusebio, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63788 ) Change subject: cpu/intel/*: Set SMM SMRR code access check bit ...................................................................... Patch Set 4: (3 comments) File src/include/cpu/intel/smm_reloc.h: https://review.coreboot.org/c/coreboot/+/63788/comment/56805718_bcf95add PS4, Line 102: SMM_CODE_ACESSS_CHK_MASK also in case bit 58 is not set, do we expected to alert the user ? https://review.coreboot.org/c/coreboot/+/63788/comment/f1f424c7_9397aa4e PS4, Line 105: } > still need the wrmsr(smm_feature) here you missed wrmsr looks like File src/soc/intel/denverton_ns/smihandler.c: https://review.coreboot.org/c/coreboot/+/63788/comment/fe8c2502_b6a3d553 PS4, Line 6: #include <cpu/intel/em64t100_save_state.h> : #include <cpu/intel/smm_reloc.h> can u also capture the order change in commit msg as well ? or prefer to do in incremental CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/63788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I254fb348483d2873917cf8c94c8b60e6f2d2c4e7 Gerrit-Change-Number: 63788 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 23 Apr 2022 07:10:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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