coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya: Set EPP to 45% for all Brya variants
by Cliff Huang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Cliff Huang. Hello Cliff Huang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62655 to review the following change. Change subject: mb/google/brya: Set EPP to 45% for all Brya variants ...................................................................... mb/google/brya: Set EPP to 45% for all Brya variants This sets EPP value to be 45% for all brya variants: BUG=b:219785001 BRANCH=firmware BRANCH=firmware-brya-14505.Bre-brya-14505.B TEST: Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62655/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 0558307..82e7c91 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -119,6 +119,10 @@ }, }" + # set EPP to 45%: 45 * 256/100 = 115 = 0x73 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x73" + device domain 0 on device ref igpu on end device ref dtt on end -- To view, visit https://review.coreboot.org/c/coreboot/+/62655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 Gerrit-Change-Number: 62655 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Yu-Ping Wu (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62471 ) Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... Patch Set 13: (1 comment) File src/soc/mediatek/common/include/soc/gpio_common.h: https://review.coreboot.org/c/coreboot/+/62471/comment/5626b05e_3ef48cfc PS13, Line 11: GPIO_DRV_INFO_NOT_IMPLEMENTED Please remove. -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 13 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:42:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0
by Rex-BC Chen (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62563 ) Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 ...................................................................... Patch Set 8: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Gerrit-Change-Number: 62563 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:41:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Rex-BC Chen (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62471 to look at the new patch set (#13). Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... soc/mediatek/mt8186: Add GPIO driving functions Add GPIO driving functions to adjust pin driving. The value of drive strength is different for each SoC, so we define GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA in MT8186. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 --- M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h 3 files changed, 354 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 13 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/bsd: Remove cb_err_t
by Yu-Ping Wu (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jakub Czapiga, Julius Werner, Tim Wawrzynczak, Felix Held. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62600 ) Change subject: commonlib/bsd: Remove cb_err_t ...................................................................... Patch Set 3: (1 comment) File src/include/cbfs.h: https://review.coreboot.org/c/coreboot/+/62600/comment/0909441e_0de8198a PS3, Line 135: enum cb_err cbfs_prog_stage_load(struct prog *prog); You may want to change the return type of legacy_romstage_select_and_load() as well, as it currently converts cb_err to int. -- To view, visit https://review.coreboot.org/c/coreboot/+/62600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Gerrit-Change-Number: 62600 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:40:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add EPP override support
by Cliff Huang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello Cliff Huang, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62654 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Add EPP override support ...................................................................... soc/intel/alderlake: Add EPP override support This update energy performance preference value to all logical CPUs. BUG=b:219785001 BRANCH=firmware BRANCH=firmware-brya-14505.Bre-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62654/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 Gerrit-Change-Number: 62654 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add EPP override support
by Cliff Huang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Cliff Huang. Hello Cliff Huang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62654 to review the following change. Change subject: soc/intel/alderlake: Add EPP override support ...................................................................... soc/intel/alderlake: Add EPP override support This update energy performance preference value to all logic CPUs. BUG=b:219785001 BRANCH=firmware BRANCH=firmware-brya-14505.Bre-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62654/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 6766406..1cca44e 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -564,6 +564,10 @@ * Default 0. Setting this to 1 enable CNVi DDR RFIM. */ bool CnviDdrRfim; + + /* Energy-Performance Preference (HWP feature) */ + bool enable_energy_perf_pref; + uint8_t energy_perf_pref_value; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 66db16b..912025b 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -122,6 +122,14 @@ /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); + const config_t *conf = config_of_soc(); + /* Set energy-performance preference */ + if (conf->enable_energy_perf_pref) { + if (check_energy_perf_cap()) { + set_energy_perf_pref(conf->energy_perf_pref_value); + } else + printk(BIOS_WARNING, "Engery Performance Preference not supported!\n"); + } /* Enable Turbo */ enable_turbo(); } @@ -132,6 +140,19 @@ smm_relocate(); } +static void pre_mp_init(void) +{ + soc_fsp_load(); + + const config_t *conf = config_of_soc(); + if (conf->enable_energy_perf_pref) { + if (check_energy_perf_cap()) { + enable_energy_perf_pref(); + } else + printk(BIOS_WARNING, "Engery Performance Preference not supported!\n"); + } +} + static void post_mp_init(void) { /* Set Max Ratio */ @@ -152,7 +173,7 @@ * that are set prior to ramstage. * Real MTRRs programming are being done after resource allocation. */ - .pre_mp_init = soc_fsp_load, + .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, -- To view, visit https://review.coreboot.org/c/coreboot/+/62654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 Gerrit-Change-Number: 62654 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/cpu/intel/common: Add support for energy performance preference (...
by Cliff Huang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Cliff Huang. Hello Cliff Huang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62653 to review the following change. Change subject: src/cpu/intel/common: Add support for energy performance preference (EPP) ...................................................................... src/cpu/intel/common: Add support for energy performance preference (EPP) This provides support to update energy performance preference value. BUG=b:219785001 BRANCH=firmware BRANCH=firmware-brya-14505.Bre-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa --- M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c M src/include/cpu/x86/msr.h 3 files changed, 66 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62653/1 diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index ef0a5d9..a29fd2e 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -47,4 +47,23 @@ */ void set_energy_perf_bias(u8 policy); +/* + * Check energy performance preference and HWP capabilities from Thermal and + * Power Management Leaf CPUID. + */ +bool check_energy_perf_cap(void); + +/* + * Set the IA32_HWP_REQUEST Energy-Performance Preference bits on the logical + * thread. 0 is a hint to the HWP to prefer performance, and 255 is a hint to + * prefer energy efficiency. + */ +void set_energy_perf_pref(u8 pref); + +/* + * Instructs the CPU to use EPP hints. This means that any energy policies set + * up in `set_energy_perf_bias` will be ignored afterwards. + */ +void enable_energy_perf_pref(void); + #endif diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 24e3eeb..77fca67 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -5,9 +5,12 @@ #include <console/console.h> #include <cpu/intel/msr.h> #include <cpu/x86/msr.h> +#include <cpu/intel/turbo.h> #include "common.h" #define CPUID_6_ECX_EPB (1 << 3) +#define CPUID_6_ENGERY_PERF_PREF (1<<10) +#define CPUID_6_HWP (1<<7) void set_vmx_and_lock(void) { @@ -182,3 +185,43 @@ msr_unset_and_set(IA32_ENERGY_PERF_BIAS, ENERGY_POLICY_MASK, epb); printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", epb); } + +/* + * Check energy performance preference and HWP capabilities from Thermal and + * Power Management Leaf CPUID + */ +bool check_energy_perf_cap(void) +{ + const u32 cap = cpuid_eax(CPUID_LEAF_PM); + if (!(cap & CPUID_6_ENGERY_PERF_PREF)) + return false; + if (!(cap & CPUID_6_HWP)) + return false; + return true; +} + +/* + * Instructs the CPU to use EPP hints. This means that any energy policies set + * up in `set_energy_perf_bias` will be ignored afterwards. + */ +void enable_energy_perf_pref(void) +{ + msr_t msr = rdmsr(IA32_PM_ENABLE); + if (!(msr.lo & HWP_ENABLE)) { + /* Package-scoped MSR */ + printk(BIOS_DEBUG, "HWP_ENABLE\n"); + msr_set(IA32_PM_ENABLE, HWP_ENABLE); + } +} + +/* + * Set the IA32_HWP_REQUEST Energy-Performance Preference bits on the logical + * thread. 0 is a hint to the HWP to prefer performance, and 255 is a hint to + * prefer energy efficiency. + * This function needs to be called when HWP_ENABLE is set. +*/ +void set_energy_perf_pref(u8 pref) +{ + msr_unset_and_set(IA32_HWP_REQUEST, IA32_HWP_REQUEST_EPP_MASK, + pref << IA32_HWP_REQUEST_EPP_SHIFT); +} diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 4d1cb68..5fcd873 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -86,8 +86,11 @@ #define IA32_VMX_MISC_MSR 0x485 #define IA32_PM_ENABLE 0x770 -#define IA32_HWP_CAPABILITIES 0x771 +#define HWP_ENABLE 0x1 +#define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 +#define IA32_HWP_REQUEST_EPP_MASK 0xff000000 +#define IA32_HWP_REQUEST_EPP_SHIFT 24 #define IA32_HWP_STATUS 0x777 #define IA32_L3_PROTECTED_WAYS 0xc85 #define IA32_SF_QOS_INFO 0xc87 -- To view, visit https://review.coreboot.org/c/coreboot/+/62653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa Gerrit-Change-Number: 62653 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Rex-BC Chen (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62471 ) Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... Patch Set 12: (1 comment) File src/soc/mediatek/mt8186/gpio.c: https://review.coreboot.org/c/coreboot/+/62471/comment/8500df74_2fc39517 PS11, Line 202: Omitted entries are all zero, same as GPIO_DRV_INFO_NOT_IMPLEMENTED > should be width=0? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 12 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:33:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0
by Rex-BC Chen (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62563 ) Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 ...................................................................... Patch Set 7: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Gerrit-Change-Number: 62563 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:32:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022