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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 )
Change subject: libpayload: Parse DDR information through coreboot tables
......................................................................
Patch Set 35:
(3 comments)
Patchset:
PS32:
> This is for getting the dram size in ramstage. […]
There seems to be very little overlap between that structure and the kind of information we care about here, so I don't think that would really work out. I guess we could consider reusing the smbios_memory_type enum if you want, though?
Patchset:
PS35:
Apologies for not getting back to this in a while, I haven't seen the end of my inbox since Perf started (and am clearly bad at prioritization).
File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h:
https://review.coreboot.org/c/coreboot/+/59193/comment/1a9595d4_e63b5c03
PS32, Line 24: 2
> I wasn't suggesting creating or using a linked-list. […]
Sorry for the confusion. This was always meant to be a variable-size array, that's why there *is* a channel_count field (see the `num_channels` above, that's exactly what that is for). All code that is reading this structure should read entries up to the number indicated in that field rather than just assume it is always 2. I didn't object to defining this array as length [2] in the struct because that made it easier to work with for now, but you are right that it should technically be length [0]. So since it already seems to be cause for confusion, let's change it to that.
There should not be a total_density field because that's just redundant with adding up the densities of all individual channels, and redundancy in informational structures is usually a bad idea (that just poses the risk of them going out of sync).
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Change subject: commonlib/bsd: Remove cb_err_t
......................................................................
Patch Set 2: Code-Review+1
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Change subject: spd/lp5: Add new part MT62F2G32D8DR-031
......................................................................
Patch Set 2: Code-Review+1
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Hello Hung-Te Lin, Jakub Czapiga, Tim Wawrzynczak, Yu-Ping Wu, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62600
to look at the new patch set (#2).
Change subject: commonlib/bsd: Remove cb_err_t
......................................................................
commonlib/bsd: Remove cb_err_t
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
---
M payloads/libpayload/include/fmap.h
M payloads/libpayload/libc/fmap.c
M payloads/libpayload/libcbfs/cbfs.c
M payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c
M payloads/libpayload/tests/libcbfs/cbfs-verification-test.c
M src/commonlib/bsd/cbfs_mcache.c
M src/commonlib/bsd/cbfs_private.c
M src/commonlib/bsd/include/commonlib/bsd/cb_err.h
M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h
M src/drivers/mipi/panel.c
M src/drivers/parade/ps8640/ps8640.c
M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
M src/include/cbfs.h
M src/include/mipi/panel.h
M src/lib/cbfs.c
M src/security/vboot/vboot_loader.c
M src/soc/mediatek/common/dsi.c
M src/soc/qualcomm/sc7180/display/dsi.c
M src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h
M tests/lib/cbfs-lookup-test.c
M tests/lib/cbfs-verification-test.c
M util/cbfstool/cbfstool.c
22 files changed, 118 insertions(+), 120 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/62600/2
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62600 )
Change subject: commonlib/bsd: Remove cb_err_t
......................................................................
Patch Set 1:
(11 comments)
File payloads/libpayload/libc/fmap.c:
https://review.coreboot.org/c/coreboot/+/62600/comment/5cd990ad_9d9025f9
PS1, Line 42: size_t *size)
> Indentation.
Done
File payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c:
https://review.coreboot.org/c/coreboot/+/62600/comment/7b9425cf_ebea0c0d
PS1, Line 60: union cbfs_mdata *mdata_out, size_t *data_offset_out)
> Indentation.
Done
https://review.coreboot.org/c/coreboot/+/62600/comment/12b5d59d_f351ea2a
PS1, Line 91: size_t *data_offset_out, struct vb2_hash *metadata_hash)
> Indentation.
Done
File payloads/libpayload/tests/libcbfs/cbfs-verification-test.c:
https://review.coreboot.org/c/coreboot/+/62600/comment/b9cd59ba_05a4e4bd
PS1, Line 57: union cbfs_mdata *mdata_out, size_t *data_offset_out)
> Indentation.
Done
https://review.coreboot.org/c/coreboot/+/62600/comment/17cc9079_f583b3bf
PS1, Line 63: size_t *data_offset_out, struct vb2_hash *metadata_hash)
> Indentation.
Done
File src/commonlib/bsd/cbfs_mcache.c:
https://review.coreboot.org/c/coreboot/+/62600/comment/580a7936_85469f2c
PS1, Line 44: size_t already_read, void *arg)
> Indentation.
Done
File src/commonlib/bsd/cbfs_private.c:
https://review.coreboot.org/c/coreboot/+/62600/comment/bf1a1b49_7bdbd89d
PS1, Line 7: const size_t devsize)
> Indentation.
Done
File src/drivers/parade/ps8640/ps8640.c:
https://review.coreboot.org/c/coreboot/+/62600/comment/7946980a_b5d299b1
PS1, Line 84: static enum cb_err ps8640_bridge_aux_request(uint8_t bus,
: uint8_t chip,
: unsigned int target_reg,
: unsigned int total_size,
: enum aux_request request,
: uint8_t *data)
> nit: Can it be changed to occupy less lines?
I think this is a valid form of formatting code, and I don't want to overrule the original author's preferences in that respect. I'm just fixing things that were shifted around by my change.
File src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c:
https://review.coreboot.org/c/coreboot/+/62600/comment/84b9100b_1de7f9e2
PS1, Line 158: static enum cb_err sn65dsi86_bridge_aux_request(uint8_t bus,
: uint8_t chip,
: unsigned int target_reg,
: unsigned int total_size,
: enum aux_request request,
: uint8_t *data)
> nit: Can it be changed to occupy less lines?
see above
File src/soc/qualcomm/sc7180/display/dsi.c:
https://review.coreboot.org/c/coreboot/+/62600/comment/b25eacb6_e6e52aa4
PS1, Line 207: static enum cb_err mdss_dsi_send_init_cmd(enum mipi_dsi_transaction type, const u8 *body, u8 len)
> > line over 96 characters […]
Done
https://review.coreboot.org/c/coreboot/+/62600/comment/9b9b8cc8_d6207f00
PS1, Line 207: static enum cb_err mdss_dsi_send_init_cmd(enum mipi_dsi_transaction type, const u8 *body, u8 len)
> > line over 96 characters […]
Done
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Change subject: mb/google/skyrim: Configure WLAN
......................................................................
Patch Set 30:
(4 comments)
File src/mainboard/google/skyrim/romstage.c:
https://review.coreboot.org/c/coreboot/+/62165/comment/f4ac2d52_64b430c3
PS29, Line 12: variant_pcie_gpio_table(&base_gpios, &base_num_gpios);
> You are getting the GPIO table, but not programming them.
Ack
File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/62165/comment/c9e176cc_7a3d0f45
PS29, Line 52: "GEVENT_14"
> Skyrim is using GPIO2/GEVENT8 for Wake on WLAN.
Ack
File src/mainboard/google/skyrim/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/62165/comment/3d2d8e21_78b7f151
PS29, Line 167: WLAN_AUX_RESET (ACTIVE LOW)
> Nit: WLAN_AUX_RESET_L. […]
Done
https://review.coreboot.org/c/coreboot/+/62165/comment/9870545f_6a66ba77
PS29, Line 169: & WWAN
> Nit: Add WWAN when you are introducing those GPIOs as well.
Done
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Hello build bot (Jenkins), Raul Rangel, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62165
to look at the new patch set (#30).
Change subject: mb/google/skyrim: Configure WLAN
......................................................................
mb/google/skyrim: Configure WLAN
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN. Mappping derived from Skyrim schematic.
BUG=b:214412172
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2
---
M src/mainboard/google/skyrim/Kconfig
A src/mainboard/google/skyrim/romstage.c
M src/mainboard/google/skyrim/variants/baseboard/Makefile.inc
M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
M src/mainboard/google/skyrim/variants/baseboard/gpio.c
M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h
6 files changed, 51 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62165/30
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Change subject: mb/google/skyrim: Configure WLAN
......................................................................
Patch Set 29:
(4 comments)
File src/mainboard/google/skyrim/romstage.c:
https://review.coreboot.org/c/coreboot/+/62165/comment/24a8a052_32ed9128
PS29, Line 12: variant_pcie_gpio_table(&base_gpios, &base_num_gpios);
You are getting the GPIO table, but not programming them.
File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/62165/comment/85aa9b1f_89e74283
PS29, Line 52: "GEVENT_14"
Skyrim is using GPIO2/GEVENT8 for Wake on WLAN.
File src/mainboard/google/skyrim/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/62165/comment/9844683a_0767d1e6
PS29, Line 167: WLAN_AUX_RESET (ACTIVE LOW)
Nit: WLAN_AUX_RESET_L. Same for line 177
https://review.coreboot.org/c/coreboot/+/62165/comment/175118be_5ce2ecae
PS29, Line 169: & WWAN
Nit: Add WWAN when you are introducing those GPIOs as well.
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 29:
(1 comment)
Patchset:
PS27:
> have you tested the case of a device being enabled, but not physically present? so what would happen […]
have you verified that this case will behave correctly?
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