Attention is currently required from: Hung-Te Lin, Rex-BC Chen.
Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62471
to look at the new patch set (#11).
Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
soc/mediatek/mt8186: Add GPIO driving functions
Add GPIO driving functions to adjust pin driving.
The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
---
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8186/gpio.c
M src/soc/mediatek/mt8186/include/soc/gpio.h
3 files changed, 356 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/11
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 )
Change subject: libpayload/pci: Split PCI interfaces as common and chip related
......................................................................
Patch Set 12:
(2 comments)
File payloads/libpayload/Kconfig:
https://review.coreboot.org/c/coreboot/+/56789/comment/400bab8a_ed0c4008
PS12, Line 418:
Similar to coreboot's implementation, could we add ECAM_MMCONF_SUPPORT and ECAM_MMCONF_BASE_ADDRESS?
File payloads/libpayload/drivers/pci_map_bus_ops.c:
PS12:
Based on Shelly's design doc [1], should we call this pci_mmio_ops.c?
[1] https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/changes/61/5786…
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Attention is currently required from: Jakub Czapiga, Julius Werner, Tim Wawrzynczak, Felix Held.
Hello Hung-Te Lin, Jakub Czapiga, Tim Wawrzynczak, Yu-Ping Wu, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62600
to look at the new patch set (#3).
Change subject: commonlib/bsd: Remove cb_err_t
......................................................................
commonlib/bsd: Remove cb_err_t
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
---
M payloads/libpayload/include/fmap.h
M payloads/libpayload/libc/fmap.c
M payloads/libpayload/libcbfs/cbfs.c
M payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c
M payloads/libpayload/tests/libcbfs/cbfs-verification-test.c
M src/commonlib/bsd/cbfs_mcache.c
M src/commonlib/bsd/cbfs_private.c
M src/commonlib/bsd/include/commonlib/bsd/cb_err.h
M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h
M src/drivers/mipi/panel.c
M src/drivers/parade/ps8640/ps8640.c
M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
M src/include/cbfs.h
M src/include/mipi/panel.h
M src/lib/cbfs.c
M src/security/vboot/vboot_loader.c
M src/soc/mediatek/common/dsi.c
M src/soc/qualcomm/sc7180/display/dsi.c
M src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h
M tests/lib/cbfs-lookup-test.c
M tests/lib/cbfs-verification-test.c
M util/cbfstool/cbfstool.c
22 files changed, 119 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/62600/3
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Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62586 )
Change subject: mb/google/brya/var/primus{4es}: add enable pin to rtd3-cold
......................................................................
mb/google/brya/var/primus{4es}: add enable pin to rtd3-cold
Currently the BayHub eMMC controller is only going into its reset
state when the RTD3 sequence is initiated. This causes it to
still consume too much power in suspend states. This CL adds the
power enable GPIO into the RTD3 sequence as well, which will turn
off the eMMC controller (a true D3cold state) during the RTD3
sequence.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 100 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/brya/variants/primus/overridetree.cb
M src/mainboard/google/brya/variants/primus4es/overridetree.cb
2 files changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index 36fee91..6b88822 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -144,6 +144,7 @@
device ref pcie_rp3 on
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
register "srcclk_pin" = "6"
device generic 0 alias emmc_rtd3 on end
end
diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
index 77218b0..d6400c2 100644
--- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
@@ -138,6 +138,7 @@
device ref pcie_rp3 on
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
register "srcclk_pin" = "6"
device generic 0 alias emmc_rtd3 on end
end
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62542 )
Change subject: spd/lp5: Add new part MT62F2G32D8DR-031
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
You may need another rebase. But otherwise this CL LGTM
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