coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake: Add EPP override support
by Cliff Huang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello Cliff Huang, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62654 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Add EPP override support ...................................................................... soc/intel/alderlake: Add EPP override support This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. BUG=b:219785001 BRANCH=firmware BRANCH=firmware-brya-14505.Bre-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62654/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 Gerrit-Change-Number: 62654 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: prog_loader: Change legacy_romstage_select_and_load() to return cb_err
by Yu-Ping Wu (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62656 ) Change subject: prog_loader: Change legacy_romstage_select_and_load() to return cb_err ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/bootblock_normal.c: https://review.coreboot.org/c/coreboot/+/62656/comment/cd5186fa_7feb7edc PS1, Line 15: int enum cb_err -- To view, visit https://review.coreboot.org/c/coreboot/+/62656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5510d05953fe8c0e2cb511f01f862b66ced154ae Gerrit-Change-Number: 62656 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:01:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Pass dram info to cbmem
by Rex-BC Chen (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Xi Chen, Hung-Te Lin, Paul Menzel, Xixi Chen, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Pass dram info to cbmem ...................................................................... Patch Set 17: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/beddb76e_d0029e2e PS16, Line 109: /* LPDDR4X */ > Could be removed now. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 17 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:01:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Rex-BC Chen (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62471 ) Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... Patch Set 15: (1 comment) File src/soc/mediatek/mt8186/gpio.c: https://review.coreboot.org/c/coreboot/+/62471/comment/2b343041_8b9b2016 PS14, Line 176: [164] = { 0, 0, 0, }, > /* 164 is unimplemented */ Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 15 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:59:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0
by Rex-BC Chen (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62563 ) Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 ...................................................................... Patch Set 10: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Gerrit-Change-Number: 62563 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:58:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Rex-BC Chen (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62471 to look at the new patch set (#15). Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... soc/mediatek/mt8186: Add GPIO driving functions Add GPIO driving functions to adjust pin driving. The value of drive strength is different for each SoC, so we define GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA in MT8186. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 --- M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h 3 files changed, 352 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 15 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/bsd: Remove cb_err_t
by Julius Werner (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jakub Czapiga, Tim Wawrzynczak, Yu-Ping Wu, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62600 ) Change subject: commonlib/bsd: Remove cb_err_t ...................................................................... Patch Set 3: (1 comment) File src/include/cbfs.h: https://review.coreboot.org/c/coreboot/+/62600/comment/12bde32b_75e4e11b PS3, Line 135: enum cb_err cbfs_prog_stage_load(struct prog *prog); > You may want to change the return type of legacy_romstage_select_and_load() as well, as it currently […] Done in follow-up. -- To view, visit https://review.coreboot.org/c/coreboot/+/62600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Gerrit-Change-Number: 62600 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:56:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: prog_loader: Change legacy_romstage_select_and_load() to return cb_err
by Julius Werner (Code Review) 08 Mar '22

08 Mar '22

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62656 ) Change subject: prog_loader: Change legacy_romstage_select_and_load() to return cb_err ...................................................................... prog_loader: Change legacy_romstage_select_and_load() to return cb_err This is passing through a cb_err from cbfs_prog_stage_load(), so it should be declared to return that as well. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I5510d05953fe8c0e2cb511f01f862b66ced154ae --- M src/arch/x86/bootblock_normal.c M src/include/program_loading.h M src/lib/prog_loaders.c 3 files changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62656/1 diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 9341ac3..873fb3e 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -24,8 +24,8 @@ if (do_normal_boot()) { romstage->name = boot_candidate; - if (!cbfs_prog_stage_load(romstage)) - return 0; + if (cbfs_prog_stage_load(romstage) == CB_SUCCESS) + return CB_SUCCESS; } romstage->name = get_fallback(boot_candidate); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index ba42465..7ff55fc 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -5,8 +5,7 @@ #include <bootmem.h> #include <commonlib/bsd/cbfs_serialized.h> #include <commonlib/region.h> -#include <stdint.h> -#include <stddef.h> +#include <types.h> enum { /* Last segment of program. Can be used to take different actions for @@ -139,7 +138,7 @@ void run_romstage(void); /* Runtime selector for CBFS_PREFIX of romstage. */ -int legacy_romstage_select_and_load(struct prog *romstage); +enum cb_err legacy_romstage_select_and_load(struct prog *romstage); /************************ * RAMSTAGE LOADING * diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 878f729e..04209ff 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -27,7 +27,7 @@ timestamp_add_now(TS_START_COPYROM); if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) { - if (legacy_romstage_select_and_load(&romstage)) + if (legacy_romstage_select_and_load(&romstage) != CB_SUCCESS) goto fail; } else { if (cbfs_prog_stage_load(&romstage)) -- To view, visit https://review.coreboot.org/c/coreboot/+/62656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5510d05953fe8c0e2cb511f01f862b66ced154ae Gerrit-Change-Number: 62656 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brask/variants/moli: init overridetree for moli
by Zhuohao Lee (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Raihow Shi, Felix Held. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62321 ) Change subject: mb/google/brask/variants/moli: init overridetree for moli ...................................................................... Patch Set 15: (1 comment) File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62321/comment/37ef955d_5de1bbcc PS9, Line 2: field AUDIO 0 2 : option AUDIO_UNKNOWN 0 : option NAU88L25B_I2S 1 : end > Ok,I remove it. Since you have removed this, please add register "CnviBtAudioOffload" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/62321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Gerrit-Change-Number: 62321 Gerrit-PatchSet: 15 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:55:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Set EPP to 45% for all Brya variants
by Cliff Huang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Cliff Huang, Tim Wawrzynczak. Hello Cliff Huang, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62655 to look at the new patch set (#3). Change subject: mb/google/brya: Set EPP to 45% for all Brya variants ...................................................................... mb/google/brya: Set EPP to 45% for all Brya variants This sets EPP value to be 45% for all brya variants: BUG=b:219785001 BRANCH=firmware BRANCH=firmware-brya-14505.Bre-brya-14505.B TEST: Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62655/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 Gerrit-Change-Number: 62655 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022