coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/mediatek: Pass dram info to cbmem
by build bot (Jenkins) (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Xi Chen, Hung-Te Lin, Paul Menzel, Xixi Chen, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Pass dram info to cbmem ...................................................................... Patch Set 17: (2 comments) File src/soc/mediatek/common/memory.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143424): https://review.coreboot.org/c/coreboot/+/61334/comment/f0189491_4cb7dc98 PS17, Line 112: for (unsigned int i = 0; i < p->num_channels; ++i) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143424): https://review.coreboot.org/c/coreboot/+/61334/comment/b3cfa2b8_a62b182c PS17, Line 130: sizeof(curr_dram_info) + sizeof(curr_dram_info.channel) * CHANNEL_MAX); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 17 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:23:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8186: Get dram size from CBMEM_ID_MEMINFO
by Xixi Chen (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Get dram size from CBMEM_ID_MEMINFO ...................................................................... Patch Set 10: (1 comment) File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/54c8165b_f0398ec0 PS8, Line 20: total_density > depends on https://review.coreboot. […] Adding all channel density size to total_density. -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 10 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:21:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Enable PCIe support
by Yu-Ping Wu (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Paul Menzel, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56793 ) Change subject: soc/mediatek/mt8195: Enable PCIe support ...................................................................... Patch Set 21: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Gerrit-Change-Number: 56793 Gerrit-PatchSet: 21 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:10:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add driver to configure PCIe
by Yu-Ping Wu (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56792 ) Change subject: soc/mediatek/mt8195: Add driver to configure PCIe ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Gerrit-Change-Number: 56792 Gerrit-PatchSet: 20 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:09:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Yu-Ping Wu (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Shelley Chen, Furquan Shaikh, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 19 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:09:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Set EPP to 45% for all Brya variants
by build bot (Jenkins) (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62655 ) Change subject: mb/google/brya: Set EPP to 45% for all Brya variants ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143420): https://review.coreboot.org/c/coreboot/+/62655/comment/b611b3a9_9916ab9e PS1, Line 122: # set EPP to 45%: 45 * 256/100 = 115 = 0x73 trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/62655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 Gerrit-Change-Number: 62655 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:08:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Jianjun Wang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 10: (1 comment) File src/soc/mediatek/mt8195/bootblock.c: https://review.coreboot.org/c/coreboot/+/62359/comment/ca2c00c2_13d8204e PS9, Line 18: : if (CONFIG(PCI)) : mtk_pcie_pre_init(); > I wonder if we can move this to bootblock_mainboard_init Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:07:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: cbmem_console: Drop loglevel markers from snapshot
by Yu-Ping Wu (Code Review) 08 Mar '22

08 Mar '22

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62506 ) Change subject: libpayload: cbmem_console: Drop loglevel markers from snapshot ...................................................................... Patch Set 2: (1 comment) File payloads/libpayload/drivers/cbmem_console.c: https://review.coreboot.org/c/coreboot/+/62506/comment/4fbce47c_c17fa469 PS1, Line 120: /* Slight memory corruption may occur between reboots and give us a few : unprintable characters like '\0'. Replace them with '?' on output. */ : for (cursor = 0; cursor < size; cursor++) : if (!isprint(console_c[cursor]) && !isspace(console_c[cursor])) : console_c[cursor] = '?'; > to add an argument to this function (bool keep_markers) I'm fine with that. -- To view, visit https://review.coreboot.org/c/coreboot/+/62506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9e5d464508320cf43ea572d62896d38c2a128d Gerrit-Change-Number: 62506 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:07:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add driver to configure PCIe
by Jianjun Wang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56792 ) Change subject: soc/mediatek/mt8195: Add driver to configure PCIe ...................................................................... Patch Set 20: (1 comment) File src/soc/mediatek/mt8195/pcie.c: https://review.coreboot.org/c/coreboot/+/56792/comment/1ecf83ec_c94c4049 PS19, Line 23: /* MMIO range (64MB): 0x20000000 ~ 0x24000000 */ : /* Some devices still need io ranges, reserve 16MB for compatibility */ : static struct mtk_pcie_mmio_res pcie_mmio_res_io = { : .cpu_addr = 0x20000000, : .pci_addr = 0x20000000, : .size = 16 * MiB, : .type = IORESOURCE_IO, : }; : : static struct mtk_pcie_mmio_res pcie_mmio_res_mem = { : .cpu_addr = 0x21000000, : .pci_addr = 0x21000000, : .size = 48 * MiB, : .type = IORESOURCE_MEM, : }; > I agree. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Gerrit-Change-Number: 56792 Gerrit-PatchSet: 20 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:06:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Shelley Chen, Furquan Shaikh, Paul Menzel, Angel Pons. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 19: (1 comment) File src/soc/mediatek/common/include/soc/pcie_common.h: https://review.coreboot.org/c/coreboot/+/56791/comment/2366946f_ed92a578 PS18, Line 20: struct mtk_pcie_mmio_res *mmio_res_io; : struct mtk_pcie_mmio_res *mmio_res_mem; > I think you can use read-only pointers (pointers to const) here: […] Done, thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 19 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:05:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022