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Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62645/comment/40fa873a_1c9d7ace
PS6, Line 30: MAULIK V VAGHELA
> Is your name in `git config` set to all caps?
Yes, it seems like that.
Thank you for pointing out, Let me correct it.
Patchset:
PS6:
> Thanks Maulik!! This is nice cleanup 😊
Thank you Tim :)
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62645
to look at the new patch set (#7).
Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case
......................................................................
soc/intel/adl/chip.h: Convert all camel case variables to snake case
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.
By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.
During renaming process, this patch also removes unused variables
listed below:
-> SataEnable // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used
Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.
BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.
Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/brya/variants/agah/overridetree.cb
M src/mainboard/google/brya/variants/anahera/overridetree.cb
M src/mainboard/google/brya/variants/anahera4es/overridetree.cb
M src/mainboard/google/brya/variants/banshee/overridetree.cb
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
M src/mainboard/google/brya/variants/brask/variant.c
M src/mainboard/google/brya/variants/brya0/overridetree.cb
M src/mainboard/google/brya/variants/brya0/variant.c
M src/mainboard/google/brya/variants/brya4es/overridetree.cb
M src/mainboard/google/brya/variants/brya4es/variant.c
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
M src/mainboard/google/brya/variants/felwinter/variant.c
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/gimble/variant.c
M src/mainboard/google/brya/variants/gimble4es/overridetree.cb
M src/mainboard/google/brya/variants/gimble4es/variant.c
M src/mainboard/google/brya/variants/kano/overridetree.cb
M src/mainboard/google/brya/variants/kano/variant.c
M src/mainboard/google/brya/variants/nereid/overridetree.cb
M src/mainboard/google/brya/variants/nivviks/overridetree.cb
M src/mainboard/google/brya/variants/primus/overridetree.cb
M src/mainboard/google/brya/variants/primus4es/overridetree.cb
M src/mainboard/google/brya/variants/redrix/overridetree.cb
M src/mainboard/google/brya/variants/redrix4es/overridetree.cb
M src/mainboard/google/brya/variants/taeko/overridetree.cb
M src/mainboard/google/brya/variants/taeko4es/overridetree.cb
M src/mainboard/google/brya/variants/taniks/overridetree.cb
M src/mainboard/google/brya/variants/vell/overridetree.cb
M src/mainboard/google/brya/variants/volmar/overridetree.cb
M src/mainboard/google/brya/variants/volmar/variant.c
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/adlrvp/devicetree_n.cb
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
M src/mainboard/prodrive/atlas/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
41 files changed, 284 insertions(+), 279 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62645/7
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 )
Change subject: lib: Add a mutex
......................................................................
Patch Set 15:
(1 comment)
Patchset:
PS15:
Well I am generally against direct replacement of spinlock with mutex like suggested in your followup work, so I cannot really give this a positive review score. Does not prevent others from doing that.
There are CB:60253 and CB:60280 available as alternative approach to solve COOP_MULTITASKING deadlock.
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Change subject: soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case
......................................................................
Patch Set 6: Code-Review+2
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Hello Hung-Te Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#11).
Change subject: src/mediatek/mt8186: Get dram size from CBMEM_ID_MEMINFO
......................................................................
src/mediatek/mt8186: Get dram size from CBMEM_ID_MEMINFO
Originally, dram size is set to 4GB by default. To support different
dram size, should update from CBMEM.
BUG=b:206014043
TEST=Build pass on Kingler
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com>
Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5
---
M src/soc/mediatek/mt8186/emi.c
1 file changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62065/11
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Hello Xi Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek: Pass dram info to cbmem
......................................................................
soc/mediatek: Pass dram info to cbmem
Pass dram_info struct from coreboot to depthcharge using payload.
BUG=b:206014043
TEST=Build pass on Kingler
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com>
Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a
---
M src/soc/mediatek/common/memory.c
M src/soc/mediatek/mt8186/Makefile.inc
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8195/Makefile.inc
4 files changed, 50 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/61334/18
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Change subject: src/mediatek/mt8186: Get dram size from CBMEM_ID_MEMINFO
......................................................................
Patch Set 10:
(1 comment)
File src/soc/mediatek/mt8186/emi.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143425):
https://review.coreboot.org/c/coreboot/+/62065/comment/b5e123ac_1ba91ae5
PS10, Line 21: for (unsigned int i = 0; i < mc->num_channels; ++i) {
braces {} are not necessary for single statement blocks
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