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Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/denverton_ns: enable Denverton to use common LPC code
......................................................................
soc/intel/denverton_ns: enable Denverton to use common LPC code
Use Intel common SoC LPC code for Denverton refactor
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: I46e55e5cdb9b8063575fe1ad7a53217ead9822e2
---
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/denverton_ns/Kconfig
A src/soc/intel/denverton_ns/include/soc/irq.h
M src/soc/intel/denverton_ns/include/soc/p2sb.h
A src/soc/intel/denverton_ns/include/soc/pcr_ids.h
M src/soc/intel/denverton_ns/lpc.c
6 files changed, 150 insertions(+), 137 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/61019/12
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Change subject: soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62766/comment/2d560b59_c57bec09
PS1, Line 7: soc/intel/tgl: Set DIMM_SPD_SIZE to 512
> Maybe: […]
Done
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Change subject: soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62766/comment/62d9042e_697e0daf
PS1, Line 9: All mainboards
> All *Tiger Lake* mainboards
already clear from the heading, which limits the change to soc/intel/tgl, but ok...
https://review.coreboot.org/c/coreboot/+/62766/comment/95c5d6ca_18896026
PS1, Line 10: the SoC
> the *Tiger Lake* SoC
the context should be clear enough now
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Hello Felix Singer, Tim Crawford, build bot (Jenkins), Sean Rhodes, Jeremy Soller, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
......................................................................
soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.
Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/google/deltaur/Kconfig
M src/mainboard/google/volteer/Kconfig
M src/mainboard/intel/tglrvp/Kconfig
M src/mainboard/starlabs/labtop/Kconfig
M src/mainboard/system76/darp7/Kconfig
M src/mainboard/system76/galp5/Kconfig
M src/mainboard/system76/gaze16/Kconfig
M src/mainboard/system76/lemp10/Kconfig
M src/mainboard/system76/oryp8/Kconfig
M src/soc/intel/tigerlake/Kconfig
10 files changed, 3 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/62766/2
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Change subject: soc/intel/tgl: Set DIMM_SPD_SIZE to 512
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62766/comment/fbc66cc9_562de216
PS1, Line 7: soc/intel/tgl: Set DIMM_SPD_SIZE to 512
Maybe:
> Move DIMM_SPD_SIZE from mainboard to SOC config
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Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62723/comment/1ed8696b_d7894950
PS2, Line 9: This change abstracts the TCSS access through IOE P2SB on Meteor Lake.
> Apart from the existing common code Kconfig _TCSS_REG_ACCESS_REGBAR, this change only adds the TCSS […]
I still do not fully understand, why the common code needs to be adapted, and what changed in Meteor Lake. But I let more knowledgable people review.
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Change subject: soc/intel/tgl: Set DIMM_SPD_SIZE to 512
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/tgl: Set DIMM_SPD_SIZE to 512
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62766/comment/ba3f6d44_4e5733ed
PS1, Line 9: All mainboards
All *Tiger Lake* mainboards
https://review.coreboot.org/c/coreboot/+/62766/comment/cf2fc232_138ad36f
PS1, Line 10: the SoC
the *Tiger Lake* SoC
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Hello build bot (Jenkins), Wonkyu Kim, Noga Smith, Stefan Reinauer, Tim Wawrzynczak, Dossym Nurmukhanov, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: util/ifdtool: Add Meteor Lake platform support under IFDv2
......................................................................
util/ifdtool: Add Meteor Lake platform support under IFDv2
BUG=b:224325352
TEST=Able to build ifdtool.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I3564efa27d0271286435284e745458aada987008
---
M util/ifdtool/ifdtool.c
M util/ifdtool/ifdtool.h
2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/61274/5
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I'd like you to reexamine a change. Please visit
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Change subject: util/ifdtool: Add Meteor Lake platform support under IFDv2
......................................................................
util/ifdtool: Add Meteor Lake platform support under IFDv2
BUG=b:b/224325352
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Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I3564efa27d0271286435284e745458aada987008
---
M util/ifdtool/ifdtool.c
M util/ifdtool/ifdtool.h
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