coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/common: Configure TCSS access through IOE P2SB
by Subrata Banik (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: John Zhao, Paul Menzel, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62723 ) Change subject: soc/intel/common: Configure TCSS access through IOE P2SB ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/62723/comment/27e1729e_4bd0f1c1 PS3, Line 389: else if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI)) { : if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)) > It seems the current format to be more descriptive to differentiate the _REGBAR and _SBI. IOE_P2SB and XYZ_P2SB(TBD) are in the scope of _SBI. > > else if (CONFIG(SOC_INTEL_COMMON_BLOCK_REG_ACCESS_SBI)) { > if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)) > ioe_tcss_configure_aux_bias_pads_sbi(pads); > else if (CONFIG(SOC_INTEL_COMMON_BLOCK_XYZ_P2SB)) > xyz_tcss_configure_aux_bias_pads_sbi(pads); > } > > I have no objection to update the format if you insist on changing it. Sure, do you see in future there would be more such interface even inside `else if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI)) {` ? I would prefer to combine as suggested, if we need to add such in future, we can do it later. -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 06:53:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid
by Henry Sun (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Tony Huang, Robert Chen, Karthik Ramasubramanian. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62002 ) Change subject: mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid ...................................................................... Patch Set 14: Code-Review+1 (1 comment) Patchset: PS14: This is for new project of Landrid. related EC changes of syncing the SSFC bits define is in https://buganizer.corp.google.com/issues/222976965#comment1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906 Gerrit-Change-Number: 62002 Gerrit-PatchSet: 14 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 06:52:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/common: Add halt() after triggering wdt reset
by Yu-Ping Wu (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62752 ) Change subject: soc/mediatek/common: Add halt() after triggering wdt reset ...................................................................... Patch Set 3: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62752/comment/56bf99a9_afcdfcc5 PS3, Line 10: after we trigger watchdog reset afterwards https://review.coreboot.org/c/coreboot/+/62752/comment/2e22ce3b_275cf6ad PS3, Line 10: whole the whole File src/soc/mediatek/common/wdt.c: https://review.coreboot.org/c/coreboot/+/62752/comment/822ffd0f_097ca8a9 PS3, Line 15: a https://review.coreboot.org/c/coreboot/+/62752/comment/6fccc6a9_4630155a PS3, Line 17: which A few words could be moved to the previous line. https://review.coreboot.org/c/coreboot/+/62752/comment/06e5bb0e_ed911983 PS3, Line 18: the -- To view, visit https://review.coreboot.org/c/coreboot/+/62752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb Gerrit-Change-Number: 62752 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 06:52:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: change pmic hwcid from warning to info
by Yu-Ping Wu (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Rex-BC Chen, Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62775 ) Change subject: soc/mediatek/mt8186: change pmic hwcid from warning to info ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62775/comment/4f7c0504_d0394a1a PS1, Line 9: It's not warning logs to dump pmic hwcid The pmic hwcid dumping should not be a warning -- To view, visit https://review.coreboot.org/c/coreboot/+/62775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea Gerrit-Change-Number: 62775 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 06:47:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: change pmic hwcid from warning to info
by Rex-BC Chen (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Yu-Ping Wu, Hung-Te Lin. Rex-BC Chen has removed Hung-Te Lin from this change. ( https://review.coreboot.org/c/coreboot/+/62775 ) Change subject: soc/mediatek/mt8186: change pmic hwcid from warning to info ...................................................................... Removed reviewer Hung-Te Lin. -- To view, visit https://review.coreboot.org/c/coreboot/+/62775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea Gerrit-Change-Number: 62775 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)gmail.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/mediatek/mt8186: Add support for PMIC MT6366
by Rex-BC Chen (Code Review) 14 Mar '22

14 Mar '22

Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59245 ) Change subject: soc/mediatek/mt8186: Add support for PMIC MT6366 ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/59245/comment/e78fc8dc_b3c229c4 PS4, Line 606: BIOS_WARNING > Why is this a warning? Please change to INFO. fix in CB:62775 -- To view, visit https://review.coreboot.org/c/coreboot/+/59245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Gerrit-Change-Number: 59245 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 06:42:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Update PCIe and SATA pins for low power consumption
by Teddy Shih (Code Review) 14 Mar '22

14 Mar '22

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62776 ) Change subject: mb/google/dedede: Update PCIe and SATA pins for low power consumption ...................................................................... mb/google/dedede: Update PCIe and SATA pins for low power consumption To achieve low power consumption, we disable unused PCIe and SATA pins at beadrix/overridetree.cb according to baseboard/devicetree.cb and mainboard schematic. After we disable unused PCIe and SATA pins, the measured power consumption meets Intel reuqired low power consumption. BRANCH=dedede BUG=b:204882915 TEST=on beadrix, measured power consumption meets Intel power consumption. Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af --- M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/62776/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 9c6d931..bfd6010 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -1,7 +1,9 @@ chip soc/intel/jasperlake # USB Port Configuration + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable unused USB2P_5 and USB2N_5 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable unused USB2P_7 and USB2N_7 # Intel Common SoC Config #+-------------------+---------------------------+ @@ -73,6 +75,7 @@ device i2c 15 on end end end # I2C 0 + device pci 17.0 off end # SATA. Baseboard/devicetree.cb is off device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -86,6 +89,8 @@ device i2c 1a on end end end # I2C 4 + device pci 1c.6 off end # PCI Express Root Port 7 / SATA_0. Baseboard/devicetree.cb is off + device pci 1c.7 off end # PCI Express Root Port 8 / SATA_1 device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98360A"" -- To view, visit https://review.coreboot.org/c/coreboot/+/62776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af Gerrit-Change-Number: 62776 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: change pmic hwcid from warning to info
by Rex-BC Chen (Code Review) 14 Mar '22

14 Mar '22

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62775 ) Change subject: soc/mediatek/mt8186: change pmic hwcid from warning to info ...................................................................... soc/mediatek/mt8186: change pmic hwcid from warning to info It's not warning logs to dump pmic hwcid, so we modify it to info. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/62775/1 diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index b993a92..30ae5e0 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -821,7 +821,7 @@ static void pmic_check_hwcid(void) { - printk(BIOS_WARNING, "%s: ID = %#x\n", __func__, + printk(BIOS_INFO, "%s: ID = %#x\n", __func__, pwrap_read_field(0x8, 0xFFFF, 0)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/62775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea Gerrit-Change-Number: 62775 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/common: Add halt() after triggering wdt reset
by Rex-BC Chen (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62752 ) Change subject: soc/mediatek/common: Add halt() after triggering wdt reset ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb Gerrit-Change-Number: 62752 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 06:41:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Configure TCSS access through IOE P2SB
by John Zhao (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Subrata Banik, Paul Menzel, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62723 ) Change subject: soc/intel/common: Configure TCSS access through IOE P2SB ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/62723/comment/cdba408a_9530d20e PS3, Line 389: else if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI)) { : if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)) > else if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI) && […] It seems the current format to be more descriptive to differentiate the _REGBAR and _SBI. IOE_P2SB and XYZ_P2SB(TBD) are in the scope of _SBI. else if (CONFIG(SOC_INTEL_COMMON_BLOCK_REG_ACCESS_SBI)) { if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)) ioe_tcss_configure_aux_bias_pads_sbi(pads); else if (CONFIG(SOC_INTEL_COMMON_BLOCK_XYZ_P2SB)) xyz_tcss_configure_aux_bias_pads_sbi(pads); } I have no objection to update the format if you insist on changing it. -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 06:39:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022