coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya: set GPP_D0 to GPO and unlocked
by Eric Lai (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: YH Lin, Nick Vaccaro, Zhuohao Lee, Mark Hsieh, EricR Lai, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62739 ) Change subject: mb/google/brya: set GPP_D0 to GPO and unlocked ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/gpio.c: https://review.coreboot.org/c/coreboot/+/62739/comment/02572515_e5c16c20 PS4, Line 121: PAD_CFG_GPO try PAD_CFG_GPO_LOCK here -- To view, visit https://review.coreboot.org/c/coreboot/+/62739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Gerrit-Change-Number: 62739 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Mar 2022 07:18:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add helper function to enable BAR
by Subrata Banik (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62778 ) Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR ...................................................................... soc/intel/common/block/p2sb: Add helper function to enable BAR This patch creates a new helper function to enable P2SB BAR. `p2sb_dev_enable_bar()` takes the PCI P2SB device address (B/D/F) and BAR addresses (both high and low). BUG=b:224325352 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 --- M src/soc/intel/common/block/include/intelblocks/p2sblib.h M src/soc/intel/common/block/p2sb/Makefile.inc M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/p2sb/p2sblib.c 4 files changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/62778/1 diff --git a/src/soc/intel/common/block/include/intelblocks/p2sblib.h b/src/soc/intel/common/block/include/intelblocks/p2sblib.h index 7df528d2..17ed385 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sblib.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sblib.h @@ -10,6 +10,7 @@ #define P2SBC 0xe0 #define P2SBC_HIDE_BIT (1 << 0) +void p2sb_dev_enable_bar(pci_devfn_t dev, uint32_t low_bar, uint32_t high_bar); bool p2sb_dev_is_hidden(pci_devfn_t dev); void p2sb_dev_unhide(pci_devfn_t dev); void p2sb_dev_hide(pci_devfn_t dev); diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index dbf4545..f051120 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -1,3 +1,5 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 94db33d..f821f50 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -18,13 +18,7 @@ void p2sb_enable_bar(void) { - /* Enable PCR Base address in PCH */ - pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR); - pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); - - /* Enable P2SB MSE */ - pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + p2sb_dev_enable_bar(PCH_DEV_P2SB, P2SB_BAR, 0); } /* diff --git a/src/soc/intel/common/block/p2sb/p2sblib.c b/src/soc/intel/common/block/p2sb/p2sblib.c index faef79a..0926c8b 100644 --- a/src/soc/intel/common/block/p2sb/p2sblib.c +++ b/src/soc/intel/common/block/p2sb/p2sblib.c @@ -10,6 +10,16 @@ #include <intelblocks/pcr.h> #include <soc/pci_devs.h> +void p2sb_dev_enable_bar(pci_devfn_t dev, uint32_t low_bar, uint32_t high_bar) +{ + /* Enable PCR Base address in PCH */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, low_bar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, high_bar); + + /* Enable P2SB MSE */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + bool p2sb_dev_is_hidden(pci_devfn_t dev) { const uint16_t pci_vid = pci_read_config16(dev, PCI_VENDOR_ID); -- To view, visit https://review.coreboot.org/c/coreboot/+/62778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Gerrit-Change-Number: 62778 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC
by Subrata Banik (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62774 to look at the new patch set (#2). Change subject: soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC ...................................................................... soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC This patch refactors the current P2SB common code driver to accommodate the future SoC platform with provision of more than one P2SB IP in disaggregated die architecture. IA SoC has only one P2SB in PCH die between SKL to ADL. Starting with MTL, one more P2SB IP resides in IOE die along with SoC die (PCH die is renamed as SoC in MTL). P2SB library (p2sblib.c) is common between PCH/SoC and IOE, and p2sb.c is added only for PCH/SoC P2SB. BUG=b:224325352 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb --- M src/soc/intel/common/block/p2sb/Kconfig M src/soc/intel/common/block/p2sb/Makefile.inc 2 files changed, 16 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/62774/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb Gerrit-Change-Number: 62774 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/common: Add halt() after triggering wdt reset
by Rex-BC Chen (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62752 ) Change subject: soc/mediatek/common: Add halt() after triggering wdt reset ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62752/comment/56c44f76_e63682f7 PS3, Line 10: whole > the whole Done https://review.coreboot.org/c/coreboot/+/62752/comment/566a489a_fa6f17d2 PS3, Line 10: after we trigger watchdog reset > afterwards Done File src/soc/mediatek/common/wdt.c: https://review.coreboot.org/c/coreboot/+/62752/comment/513d585b_97765e10 PS3, Line 15: > a Done https://review.coreboot.org/c/coreboot/+/62752/comment/aea67e6e_d134d72b PS3, Line 17: which > A few words could be moved to the previous line. Done https://review.coreboot.org/c/coreboot/+/62752/comment/86325dc8_2f8e8041 PS3, Line 18: > the Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb Gerrit-Change-Number: 62752 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 07:15:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/common: Add halt() after triggering wdt reset
by Rex-BC Chen (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62752 to look at the new patch set (#4). Change subject: soc/mediatek/common: Add halt() after triggering wdt reset ...................................................................... soc/mediatek/common: Add halt() after triggering wdt reset It's more reasonable to halt when we trigger watchdog reset because the whole system should be reset afterwards. BUG=b:222217317 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb --- M src/soc/mediatek/common/wdt.c 1 file changed, 21 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/62752/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb Gerrit-Change-Number: 62752 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: change pmic hwcid from warning to info
by Rex-BC Chen (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Hung-Te Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62775 to look at the new patch set (#3). Change subject: soc/mediatek/mt8186: change pmic hwcid from warning to info ...................................................................... soc/mediatek/mt8186: change pmic hwcid from warning to info The pmic hwcid dumping should not be a warning, so we modify it to info. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/62775/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea Gerrit-Change-Number: 62775 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: change pmic hwcid from warning to info
by Yu-Ping Wu (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62775 ) Change subject: soc/mediatek/mt8186: change pmic hwcid from warning to info ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea Gerrit-Change-Number: 62775 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 07:13:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: set GPP_D0 to GPO and unlocked
by Wisley Chen (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: YH Lin, Nick Vaccaro, Eric Lai, Zhuohao Lee, Mark Hsieh, EricR Lai, Felix Held. Wisley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62739 ) Change subject: mb/google/brya: set GPP_D0 to GPO and unlocked ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/gpio.c: https://review.coreboot.org/c/coreboot/+/62739/comment/3fdbfd53_5cc43cd2 PS2, Line 122: /* D1 : ISH_GP1 ==> FP_RST_ODL */ : PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), : /* D2 : ISH_GP2 ==> EN_FP_PWR */ : PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), > Could you please try to read the value back with below command after using the kernel sysfs to outpu […] for redrix (GPP_D1/GPP_D2 in 14505.21.0) localhost ~ # echo 0 > /sys/class/gpio/gpio313/value localhost ~ # iotools mem_read32 0xfd6d0910 0x04000200 localhost ~ # echo 1 > /sys/class/gpio/gpio313/value localhost ~ # iotools mem_read32 0xfd6d0910 0x04000201 localhost ~ # echo 0 > /sys/class/gpio/gpio314/value localhost ~ # iotools mem_read32 0xfd6d0920 0x04000200 localhost ~ # echo 1 > /sys/class/gpio/gpio314/value localhost ~ # iotools mem_read32 0xfd6d0920 0x04000201 -- To view, visit https://review.coreboot.org/c/coreboot/+/62739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Gerrit-Change-Number: 62739 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Mar 2022 07:12:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: change pmic hwcid from warning to info
by Rex-BC Chen (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62775 ) Change subject: soc/mediatek/mt8186: change pmic hwcid from warning to info ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62775/comment/052e9954_6a1d68ae PS1, Line 9: It's not warning logs to dump pmic hwcid > The pmic hwcid dumping should not be a warning Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea Gerrit-Change-Number: 62775 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 06:56:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: change pmic hwcid from warning to info
by Rex-BC Chen (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Rex-BC Chen, Hung-Te Lin. Hello Yu-Ping Wu, Hung-Te Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62775 to look at the new patch set (#2). Change subject: soc/mediatek/mt8186: change pmic hwcid from warning to info ...................................................................... soc/mediatek/mt8186: change pmic hwcid from warning to info The pmic hwcid dumping should not be a warning, so we modify it to info. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/62775/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea Gerrit-Change-Number: 62775 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022