coreboot-gerrit March 2022

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Change in coreboot[master]: util/ifdtool: Add Meteor Lake platform support under IFDv2
by Felix Held (Code Review) 15 Mar '22

15 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61274 ) Change subject: util/ifdtool: Add Meteor Lake platform support under IFDv2 ...................................................................... util/ifdtool: Add Meteor Lake platform support under IFDv2 BUG=b:224325352 TEST=Able to build ifdtool. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3564efa27d0271286435284e745458aada987008 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61274 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Edward O'Callaghan: Looks good to me, but someone else must approve diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index a5c0b69..bc62b48 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -248,6 +248,7 @@ case PLATFORM_TGL: case PLATFORM_ADL: case PLATFORM_IFD2: + case PLATFORM_MTL: return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT; case PLATFORM_ICL: return CHIPSET_400_SERIES_ICE_POINT; @@ -281,6 +282,7 @@ PLATFORM_ADL, PLATFORM_SKLKBL, PLATFORM_IFD2, + PLATFORM_MTL, }; unsigned int i; @@ -1232,6 +1234,7 @@ case PLATFORM_EHL: case PLATFORM_ADL: case PLATFORM_IFD2: + case PLATFORM_MTL: /* CPU/BIOS can read descriptor and BIOS. */ fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift; @@ -1974,6 +1977,8 @@ platform = PLATFORM_ADL; } else if (!strcmp(optarg, "ifd2")) { platform = PLATFORM_IFD2; + } else if (!strcmp(optarg, "mtl")) { + platform = PLATFORM_MTL; } else { fprintf(stderr, "Unknown platform: %s\n", optarg); exit(EXIT_FAILURE); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 67f31c3..1ee76f1 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -61,6 +61,7 @@ PLATFORM_ADL, PLATFORM_IFD2, PLATFORM_DNV, + PLATFORM_MTL, }; #define LAYOUT_LINELEN 80 -- To view, visit https://review.coreboot.org/c/coreboot/+/61274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3564efa27d0271286435284e745458aada987008 Gerrit-Change-Number: 61274 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Noga Smith <nogasmith(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
by Felix Held (Code Review) 15 Mar '22

15 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62766 ) Change subject: soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig ...................................................................... soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to 512 in the SoC Kconfig and drop it from the mainboard Kconfigs. Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/deltaur/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/starlabs/labtop/Kconfig M src/mainboard/system76/darp7/Kconfig M src/mainboard/system76/galp5/Kconfig M src/mainboard/system76/gaze16/Kconfig M src/mainboard/system76/lemp10/Kconfig M src/mainboard/system76/oryp8/Kconfig M src/soc/intel/tigerlake/Kconfig 10 files changed, 3 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Tim Crawford: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index 492bcbb..eb27796 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -36,9 +36,6 @@ select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_SWITCH_ON -config DIMM_SPD_SIZE - default 512 - config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index eb8f176..4f83d1c 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -144,9 +144,6 @@ select SAR_ENABLE select USE_SAR -config DIMM_SPD_SIZE - default 512 - config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 9e63f2c..8a4c9ad 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -60,9 +60,6 @@ config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" -config DIMM_SPD_SIZE - default 512 - choice prompt "ON BOARD EC" default TGL_CHROME_EC diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig index 0f7d108..f8a5bc7 100644 --- a/src/mainboard/starlabs/labtop/Kconfig +++ b/src/mainboard/starlabs/labtop/Kconfig @@ -46,9 +46,6 @@ config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" -config DIMM_SPD_SIZE - default 512 - config DRIVER_TPM_SPI_CHIP default 2 diff --git a/src/mainboard/system76/darp7/Kconfig b/src/mainboard/system76/darp7/Kconfig index 75d8e1d..960e5ae 100644 --- a/src/mainboard/system76/darp7/Kconfig +++ b/src/mainboard/system76/darp7/Kconfig @@ -44,9 +44,6 @@ config CONSOLE_POST default y -config DIMM_SPD_SIZE - default 512 - config POST_DEVICE default n diff --git a/src/mainboard/system76/galp5/Kconfig b/src/mainboard/system76/galp5/Kconfig index bb4b2ea..98e32f7 100644 --- a/src/mainboard/system76/galp5/Kconfig +++ b/src/mainboard/system76/galp5/Kconfig @@ -43,9 +43,6 @@ config CONSOLE_POST default y -config DIMM_SPD_SIZE - default 512 - config ONBOARD_VGA_IS_PRIMARY default y diff --git a/src/mainboard/system76/gaze16/Kconfig b/src/mainboard/system76/gaze16/Kconfig index daf3302..cc96d5f 100644 --- a/src/mainboard/system76/gaze16/Kconfig +++ b/src/mainboard/system76/gaze16/Kconfig @@ -55,9 +55,6 @@ config CONSOLE_POST default y -config DIMM_SPD_SIZE - default 512 - config ONBOARD_VGA_IS_PRIMARY default y diff --git a/src/mainboard/system76/lemp10/Kconfig b/src/mainboard/system76/lemp10/Kconfig index fc8abba..a732425 100644 --- a/src/mainboard/system76/lemp10/Kconfig +++ b/src/mainboard/system76/lemp10/Kconfig @@ -44,9 +44,6 @@ config CONSOLE_POST default y -config DIMM_SPD_SIZE - default 512 - config POST_DEVICE default n diff --git a/src/mainboard/system76/oryp8/Kconfig b/src/mainboard/system76/oryp8/Kconfig index 958cda8..8e65b70 100644 --- a/src/mainboard/system76/oryp8/Kconfig +++ b/src/mainboard/system76/oryp8/Kconfig @@ -49,9 +49,6 @@ config DIMM_MAX default 4 -config DIMM_SPD_SIZE - default 512 - config ONBOARD_VGA_IS_PRIMARY default y diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 6d20112..2b673cab 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -94,6 +94,9 @@ default 16 if SOC_INTEL_TIGERLAKE_PCH_H default 8 +config DIMM_SPD_SIZE + default 512 + config DCACHE_RAM_BASE default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/62766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Gerrit-Change-Number: 62766 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/common/block: Add APL and GLK PCI IDs for HDA
by Felix Held (Code Review) 15 Mar '22

15 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61804 ) Change subject: intel/common/block: Add APL and GLK PCI IDs for HDA ...................................................................... intel/common/block: Add APL and GLK PCI IDs for HDA Add PCI ID's for APL/GLK so they can use HDA. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61804 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/common/block/hda/hda.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index b9c6290..0143a40 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -29,6 +29,8 @@ PCI_DID_INTEL_MTL_AUDIO_6, PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, + PCI_DID_INTEL_APL_AUDIO, + PCI_DID_INTEL_GLK_AUDIO, PCI_DID_INTEL_SKL_AUDIO, PCI_DID_INTEL_SKL_H_AUDIO, PCI_DID_INTEL_LWB_AUDIO, -- To view, visit https://review.coreboot.org/c/coreboot/+/61804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9 Gerrit-Change-Number: 61804 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE
by Sridhar Siricilla (Code Review) 15 Mar '22

15 Mar '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62843 ) Change subject: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE ...................................................................... soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake and Tiher Lake SoCs. It allows acces to intelbasecode/debug_feature.h for Comet Lake, Jasper Lake and Tiger Lake SoCs. TEST=Build code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/62843/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9517cee..4229c81 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -26,6 +26,7 @@ select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT + select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU config SOC_INTEL_COMETLAKE_1 bool diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 48b735e..b540a11 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -68,6 +68,7 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select SOC_INTEL_COMMON_BASECODE config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 6d20112..ddd71b8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -88,6 +88,7 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select SOC_INTEL_COMMON_BASECODE config MAX_CPUS int -- To view, visit https://review.coreboot.org/c/coreboot/+/62843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e Gerrit-Change-Number: 62843 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/efi: Clean up efi_datatype.h file
by Tim Wawrzynczak (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Subrata Banik, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62787 ) Change subject: include/efi: Clean up efi_datatype.h file ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9177814fcf41e5950ace94050356f0273f765c5 Gerrit-Change-Number: 62787 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 19:20:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update APU STT setting
by Felix Held (Code Review) 15 Mar '22

15 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62790 ) Change subject: mb/google/guybrush/var/nipperkin: update APU STT setting ...................................................................... mb/google/guybrush/var/nipperkin: update APU STT setting BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index adde71f..668c109 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -216,13 +216,13 @@ register "stt_control" = "1" register "stt_pcb_sensor_count" = "2" register "stt_min_limit" = "12000" - register "stt_m1" = "0x466" - register "stt_m2" = "0xFF3B" + register "stt_m1" = "0x04DE" + register "stt_m2" = "0x13" register "stt_m3" = "0" register "stt_m4" = "0" register "stt_m5" = "0" register "stt_m6" = "0" - register "stt_c_apu" = "0x14DA" + register "stt_c_apu" = "0xDA43" register "stt_c_gpu" = "0" register "stt_c_hs2" = "0" register "stt_alpha_apu" = "0x199A" -- To view, visit https://review.coreboot.org/c/coreboot/+/62790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 Gerrit-Change-Number: 62790 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/banshee: Add camera privacy setting
by Felix Held (Code Review) 15 Mar '22

15 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62780 ) Change subject: mb/google/brya/var/banshee: Add camera privacy setting ...................................................................... mb/google/brya/var/banshee: Add camera privacy setting Using the GPP_F19 as privacy switch for camera in banshee. BUG=b:223712143, b:216110896 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/banshee/overridetree.cb 2 files changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index 9bf6518..75a2743 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -180,8 +180,8 @@ PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - /* F19 : SRCCLKREQ6# ==> NC */ - PAD_NC(GPP_F19, NONE), + /* F19 : SRCCLKREQ6# ==> CAM_SW */ + PAD_CFG_GPI_INT(GPP_F19, NONE, PLTRST, EDGE_BOTH), /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), /* F21 : EXT_PWR_GATE2# ==> NC */ diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index 8729b3a..9601d05 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -312,6 +312,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F19)" device ref usb2_port6 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/62780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14 Gerrit-Change-Number: 62780 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/wifi/generic: Add ops to generic cnvi device
by Tim Wawrzynczak (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Paul Menzel, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62746 ) Change subject: drivers/wifi/generic: Add ops to generic cnvi device ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62746/comment/6c803b21_1c1f7693 PS1, Line 16: TEST=error message about a GENERIC 0.0 device missing read_resources is : gone. > On what device? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 Gerrit-Change-Number: 62746 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 19:19:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/wifi/generic: Add ops to generic cnvi device
by Tim Wawrzynczak (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Nick Vaccaro. Hello Varshit B Pandya, build bot (Jenkins), Subrata Banik, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62746 to look at the new patch set (#2). Change subject: drivers/wifi/generic: Add ops to generic cnvi device ...................................................................... drivers/wifi/generic: Add ops to generic cnvi device When adding properties to the Intel CNVi devices, a chip driver and a generic device are added underneath to contain the chip config properties. Currently there are no ops for this, and so a BIOS_ERR is printed that there is a device with no `read_resources` callback, which is true. Therefore, this patch adds a noop ops to this generic device. BUG=b:220639445 TEST=on google/brya0, error message about a GENERIC 0.0 device missing read_resources is gone. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 --- M src/drivers/wifi/generic/generic.c 1 file changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/62746/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 Gerrit-Change-Number: 62746 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd: Do not print part number if it is not available
by Felix Held (Code Review) 15 Mar '22

15 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62699 ) Change subject: lib/spd: Do not print part number if it is not available ...................................................................... lib/spd: Do not print part number if it is not available If the DRAM part number is not available in the SPD data (meaning filled with 0x00) do not print it in the log. Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62699 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/spd_bin.c 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 865f16c..1b236b0 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -167,8 +167,10 @@ case SPD_DRAM_DDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: - *spd_name = (const char *) &spd[DDR4_SPD_PART_OFF]; - *len = DDR4_SPD_PART_LEN; + if (spd[DDR4_SPD_PART_OFF]) { + *spd_name = (const char *) &spd[DDR4_SPD_PART_OFF]; + *len = DDR4_SPD_PART_LEN; + } break; default: *len = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/62699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee Gerrit-Change-Number: 62699 Gerrit-PatchSet: 5 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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