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Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/62064/comment/f22bbd9c_7a34f367
PS9, Line 634: && (GEN_PMCON_A <= 0xff)
> Trying to avoid SoC name in common code, once added then it will become as a trend like Intel FSP, where common code does the SoC check 😞
Agreed
> I'm trying to add new Kconfig due to maintenance and added the big comment section to explain what is the reason for this additional check.
I guess you meant `avoid`?
Is it really that much maintenance?
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Change subject: mb/google/brask/variants/moli: set eMMC pin in bootblock
......................................................................
Patch Set 5: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62770/comment/b4ca53a9_d6c96a80
PS3, Line 9: 1.add eMMC enable pin in bootblock
: 2.set eMMC reset pin unable in bootblock
> Ok, […]
I think I misread the table at first, this all looks correct.
Commit Message:
https://review.coreboot.org/c/coreboot/+/62770/comment/3c8791b6_5cf035f0
PS5, Line 10: unable
remove this word
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Change subject: mb/google/brask/variants/moli: update GPIO for moli
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Patch Set 5:
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https://review.coreboot.org/c/coreboot/+/62802/comment/1e85ccbe_e95548be
PS5, Line 9: GPIO table
version of schematics?
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Change subject: mb/hp/snb_ivb_laptops/Kconfig{,.name}: Reorder selects alphabetically
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Patch Set 2: Code-Review+2
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Change subject: mb/google/brya/var/volmar: Disable thunderbolt
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62810/comment/5c61476b_fe14a97d
PS2, Line 9: Disable thunderbolot(TBT) pcie for volmar.
Can just say something like
`Volmar does not support Thunderbolt, therefore disable all of the TBT devices in the devicetree.`
https://review.coreboot.org/c/coreboot/+/62810/comment/989df6db_a72786ec
PS2, Line 9: thunderbolot
`Thunderbolt`
File src/mainboard/google/brya/variants/volmar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62810/comment/7156af2b_204e63d4
PS2, Line 91:
Probably also need to disable
tcss_dma0 and tcss_dma1
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Change subject: ec/google/chromeec: Change loglevel prefix
......................................................................
Patch Set 1: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62823/comment/003b93f4_60acf734
PS1, Line 10: of smbios.
`in the SMBIOS table.`
https://review.coreboot.org/c/coreboot/+/62823/comment/399c6343_f3cfa4ae
PS1, Line 10: smbios.
: It' better use the "BIOS_INFO" than "BIOS_ERR"
:
remove line break between the two sentences?
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Change subject: soc/intel/common/block/cse: Change logleve prefix to WARNING
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62820/comment/75c6b2cc_3458e0ca
PS1, Line 8:
: In do_send_end_of_post(), it checks whether send eop or not.
: So, it's better to use "BIOS_WARNING" than "BIOS_ERR"
Suggestion:
```
This message is not really an error message, so BIOS_ERR is inappropriate. The message does seem more like a warning though, that the developer could have multiple Kconfigs selected to send EOP, therefore switch to BIOS_WARN instead
```
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Change subject: soc/intel/alderlake/retimer: Change loglevel prefix
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62821/comment/c6de7286_91f150ed
PS1, Line 9: It shows the ec mapped port, so change the loglevel to BIOS_INFO.
suggestion:
```
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to
BIOS_INFO instead
```
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Change subject: mb/google/brya/var/banshee: Update DPTF parameters for Banshee
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