coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify the DPTF/Fan parameters
by Felix Held (Code Review) 16 Mar '22

16 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62625 ) Change subject: mb/google/brya/var/kinox: Modify the DPTF/Fan parameters ...................................................................... mb/google/brya/var/kinox: Modify the DPTF/Fan parameters Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters. BUG=b:221180425, b:222020226, b:221182596 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kinox/overridetree.cb 1 file changed, 141 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 4168c4f..a4050ee 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -46,6 +46,147 @@ }" device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(80, 97), + TEMP_PCT(65, 93), + TEMP_PCT(58, 86), + TEMP_PCT(50, 80), + TEMP_PCT(45, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [4] = { + .target = DPTF_TEMP_SENSOR_4, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 10000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 10000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 10000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 10000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 93, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 93, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 93, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 93, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 17000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500, + }, + .pl2 = { + .min_power = 39000, + .max_power = 39000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end device ref pcie_rp7 on chip drivers/net register "customized_leds" = "0x05af" -- To view, visit https://review.coreboot.org/c/coreboot/+/62625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929 Gerrit-Change-Number: 62625 Gerrit-PatchSet: 7 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Retry MEI CSE DISABLE command
by Felix Held (Code Review) 16 Mar '22

16 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62560 ) Change subject: soc/intel/common: Retry MEI CSE DISABLE command ...................................................................... soc/intel/common: Retry MEI CSE DISABLE command As per ME BWG, the patch retries MEI CSE DISABLE command if CSE doesn't respond or sends the garbled response. It retries the command additionally 2 more times. TEST=build and boot the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62560 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 10 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index c6b5277..a8c8bbd 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -34,7 +34,7 @@ } } -static bool cse_disable_mei_bus(void) +static enum cse_cmd_result cse_disable_mei_bus(void) { struct bus_disable_message { uint8_t command; @@ -49,18 +49,22 @@ } __packed reply = {}; size_t reply_sz = sizeof(reply); + enum cse_tx_rx_status ret; - if (heci_send_receive(&msg, sizeof(msg), &reply, &reply_sz, HECI_MEI_ADDR)) { + printk(BIOS_DEBUG, "HECI, Sending MEI BIOS DISABLE command\n"); + ret = heci_send_receive(&msg, sizeof(msg), &reply, &reply_sz, HECI_MEI_ADDR); + + if (ret) { printk(BIOS_ERR, "HECI: Failed to Disable MEI bus\n"); - return false; + return decode_heci_send_receive_error(ret); } if (reply.status) { printk(BIOS_ERR, "HECI: MEI_Bus_Disable Failed (status: %d)\n", reply.status); - return false; + return CSE_CMD_RESULT_ERROR; } - return true; + return CSE_CMD_RESULT_SUCCESS; } static enum cse_cmd_result cse_send_eop(void) @@ -158,7 +162,7 @@ */ static void cse_handle_eop_error(void) { - if (!cse_disable_mei_bus()) + if (cse_send_cmd_retries(cse_disable_mei_bus)) die("Failed to disable MEI bus while recovering from EOP error\n" "Preventing system from booting into an insecure state.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/62560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb Gerrit-Change-Number: 62560 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Retry END_OF_POST command
by Felix Held (Code Review) 16 Mar '22

16 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62192 ) Change subject: soc/intel/common: Retry END_OF_POST command ...................................................................... soc/intel/common: Retry END_OF_POST command As per ME BWG, the patch retries END_OF_POST command if CSE doesn't respond or sends the garbled response. It retries the command additionally 2 more times. BUG=b:200251277 TEST=Verify EOP retry mechanism for brya board. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62192 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 33 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index bc6d837..c6b5277 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -11,13 +11,29 @@ #include <timestamp.h> #include <types.h> +#define CSE_MAX_RETRY_CMD 3 + enum cse_cmd_result { CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED, CSE_CMD_RESULT_SUCCESS, CSE_CMD_RESULT_ERROR, CSE_CMD_RESULT_DISABLED, + CSE_CMD_RESULT_RETRY, }; +static enum cse_cmd_result decode_heci_send_receive_error(enum cse_tx_rx_status ret) +{ + switch (ret) { + case CSE_TX_ERR_CSE_NOT_READY: + case CSE_RX_ERR_CSE_NOT_READY: + case CSE_RX_ERR_RESP_LEN_MISMATCH: + case CSE_RX_ERR_TIMEOUT: + return CSE_CMD_RESULT_RETRY; + default: + return CSE_CMD_RESULT_ERROR; + } +} + static bool cse_disable_mei_bus(void) { struct bus_disable_message { @@ -49,6 +65,7 @@ static enum cse_cmd_result cse_send_eop(void) { + enum cse_tx_rx_status ret; enum { EOP_REQUESTED_ACTION_CONTINUE = 0, EOP_REQUESTED_ACTION_GLOBAL_RESET = 1, @@ -98,10 +115,9 @@ printk(BIOS_INFO, "HECI: Sending End-of-Post\n"); - if (heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR)) { - printk(BIOS_ERR, "HECI: EOP send/receive fail\n"); - return CSE_CMD_RESULT_ERROR; - } + ret = heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR); + if (ret) + return decode_heci_send_receive_error(ret); if (resp.hdr.result) { printk(BIOS_ERR, "HECI: EOP Resp Failed: %u\n", resp.hdr.result); @@ -123,6 +139,18 @@ } } +static enum cse_cmd_result cse_send_cmd_retries(enum cse_cmd_result (*cse_send_command)(void)) +{ + size_t retry; + enum cse_cmd_result ret; + for (retry = 0; retry < CSE_MAX_RETRY_CMD; retry++) { + ret = cse_send_command(); + if (ret != CSE_CMD_RESULT_RETRY) + break; + } + return ret; +} + /* * On EOP error, the BIOS is required to send an MEI bus disable message to the * CSE, followed by disabling all MEI devices. After successfully completing @@ -193,7 +221,7 @@ set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); timestamp_add_now(TS_ME_END_OF_POST_START); - handle_cse_eop_result(cse_send_eop()); + handle_cse_eop_result(cse_send_cmd_retries(cse_send_eop)); timestamp_add_now(TS_ME_END_OF_POST_END); set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); -- To view, visit https://review.coreboot.org/c/coreboot/+/62192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Gerrit-Change-Number: 62192 Gerrit-PatchSet: 14 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: 3rdparty/amd_blobs: advance submodule pointer
by Felix Held (Code Review) 16 Mar '22

16 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62811 ) Change subject: 3rdparty/amd_blobs: advance submodule pointer ...................................................................... 3rdparty/amd_blobs: advance submodule pointer This adds the following commits: * a069321 cezanne: Update SMU firmware to 64.62.0 * d8a51cb cezanne: Upgrade ABL to 0x22146070 Change-Id: I066252eda56b8b62db420cbcfc95c97875a3b6d1 Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62811 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 9e8f457..a069321 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 9e8f457edcc359552a5d0113568a2d1670009178 +Subproject commit a0693217d2fea9f3c05f6d96008c1ad301ed69e6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I066252eda56b8b62db420cbcfc95c97875a3b6d1 Gerrit-Change-Number: 62811 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: PCI: Remove global variable
by Felix Held (Code Review) 16 Mar '22

16 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62800 ) Change subject: soc/mediatek: PCI: Remove global variable ...................................................................... soc/mediatek: PCI: Remove global variable Remove global variable and use 'pcidev_path_on_root()' to get the base address of PCIe controller. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62800 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/pcie.c 1 file changed, 29 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index 4ed8b93..c46b53f 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -65,8 +65,6 @@ #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) -static const struct mtk_pcie_config *pcie_ctrl; - /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ static const char *const ltssm_str[] = { "detect.quiet", /* 0x00 */ @@ -98,17 +96,34 @@ "hotreset", /* 0x1A */ }; +static uintptr_t mtk_pcie_get_controller_base(pci_devfn_t devfn) +{ + struct device *root_dev; + const mtk_soc_config_t *config; + static uintptr_t base = 0; + + if (!base) { + root_dev = pcidev_path_on_root(devfn); + config = config_of(root_dev); + base = config->pcie_config.base; + } + + return base; +} + volatile union pci_bank *pci_map_bus(pci_devfn_t dev) { u32 val, devfn, bus; + uintptr_t base; devfn = PCI_DEV2DEVFN(dev); bus = PCI_DEV2SEGBUS(dev); val = PCIE_CFG_HEADER(bus, devfn); - write32p(pcie_ctrl->base + PCIE_CFGNUM_REG, val); + base = mtk_pcie_get_controller_base(dev); + write32p(base + PCIE_CFGNUM_REG, val); - return (void *)(pcie_ctrl->base + PCIE_CFG_OFFSET_ADDR); + return (void *)(base + PCIE_CFG_OFFSET_ADDR); } static int mtk_pcie_set_trans_window(struct device *dev, uintptr_t table, @@ -197,35 +212,34 @@ void mtk_pcie_domain_enable(struct device *dev) { const mtk_soc_config_t *config = config_of(dev); + const struct mtk_pcie_config *conf = &config->pcie_config; const char *ltssm_state; size_t tries = 0; uint32_t val; - pcie_ctrl = &config->pcie_config; - /* Set as RC mode */ - val = read32p(pcie_ctrl->base + PCIE_SETTING_REG); + val = read32p(conf->base + PCIE_SETTING_REG); val |= PCIE_RC_MODE; - write32p(pcie_ctrl->base + PCIE_SETTING_REG, val); + write32p(conf->base + PCIE_SETTING_REG, val); /* Set class code */ - val = read32p(pcie_ctrl->base + PCIE_PCI_IDS_1); + val = read32p(conf->base + PCIE_PCI_IDS_1); val &= ~GENMASK(31, 8); val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - write32p(pcie_ctrl->base + PCIE_PCI_IDS_1, val); + write32p(conf->base + PCIE_PCI_IDS_1, val); /* Mask all INTx interrupts */ - val = read32p(pcie_ctrl->base + PCIE_INT_ENABLE_REG); + val = read32p(conf->base + PCIE_INT_ENABLE_REG); val &= ~PCIE_INTX_ENABLE; - write32p(pcie_ctrl->base + PCIE_INT_ENABLE_REG, val); + write32p(conf->base + PCIE_INT_ENABLE_REG, val); /* De-assert reset signals */ - mtk_pcie_reset(pcie_ctrl->base + PCIE_RST_CTRL_REG, false); + mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false); if (!retry(100, - (tries++, read32p(pcie_ctrl->base + PCIE_LINK_STATUS_REG) & + (tries++, read32p(conf->base + PCIE_LINK_STATUS_REG) & PCIE_CTRL_LINKUP), mdelay(1))) { - val = read32p(pcie_ctrl->base + PCIE_LTSSM_STATUS_REG); + val = read32p(conf->base + PCIE_LTSSM_STATUS_REG); ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ? "Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)]; printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/62800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9 Gerrit-Change-Number: 62800 Gerrit-PatchSet: 3 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Add chip config for setting PCIe config
by Felix Held (Code Review) 16 Mar '22

16 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62791 ) Change subject: soc/mediatek: Add chip config for setting PCIe config ...................................................................... soc/mediatek: Add chip config for setting PCIe config Add chip config for setting PCIe config. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c A src/soc/mediatek/mt8195/chip.h M src/soc/mediatek/mt8195/include/soc/pcie.h A src/soc/mediatek/mt8195/include/soc/soc_chip.h M src/soc/mediatek/mt8195/pcie.c 6 files changed, 77 insertions(+), 93 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h index d737c9d..0f02ab7 100644 --- a/src/soc/mediatek/common/include/soc/pcie_common.h +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -13,12 +13,10 @@ unsigned long type; }; -struct mtk_pcie_controller { +struct mtk_pcie_config { uintptr_t base; /* MAC physical address */ - int (*phy_init)(void); - void (*reset)(uintptr_t base, bool enable); - const struct mtk_pcie_mmio_res *mmio_res_io; - const struct mtk_pcie_mmio_res *mmio_res_mem; + const struct mtk_pcie_mmio_res mmio_res_io; + const struct mtk_pcie_mmio_res mmio_res_mem; }; void mtk_pcie_domain_read_resources(struct device *dev); diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index c05db8c..4ed8b93 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -13,6 +13,7 @@ #include <soc/addressmap.h> #include <soc/pcie.h> #include <soc/pcie_common.h> +#include <soc/soc_chip.h> #include <stdlib.h> #include <types.h> @@ -64,7 +65,7 @@ #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) -static struct mtk_pcie_controller pcie_ctrl; +static const struct mtk_pcie_config *pcie_ctrl; /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ static const char *const ltssm_str[] = { @@ -105,56 +106,9 @@ bus = PCI_DEV2SEGBUS(dev); val = PCIE_CFG_HEADER(bus, devfn); - write32p(pcie_ctrl.base + PCIE_CFGNUM_REG, val); + write32p(pcie_ctrl->base + PCIE_CFGNUM_REG, val); - return (void *)(pcie_ctrl.base + PCIE_CFG_OFFSET_ADDR); -} - -static int mtk_pcie_startup_port(struct mtk_pcie_controller *ctrl) -{ - uint32_t val; - size_t tries = 0; - const char *ltssm_state; - - /* Set as RC mode */ - val = read32p(ctrl->base + PCIE_SETTING_REG); - val |= PCIE_RC_MODE; - write32p(ctrl->base + PCIE_SETTING_REG, val); - - /* Set class code */ - val = read32p(ctrl->base + PCIE_PCI_IDS_1); - val &= ~GENMASK(31, 8); - val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - write32p(ctrl->base + PCIE_PCI_IDS_1, val); - - /* Mask all INTx interrupts */ - val = read32p(ctrl->base + PCIE_INT_ENABLE_REG); - val &= ~PCIE_INTX_ENABLE; - write32p(ctrl->base + PCIE_INT_ENABLE_REG, val); - - if (!ctrl->reset) { - printk(BIOS_ERR, "%s: Missing reset function\n", __func__); - return -1; - } - - /* De-assert reset signals */ - ctrl->reset(ctrl->base + PCIE_RST_CTRL_REG, false); - - if (!retry(100, - (tries++, read32p(ctrl->base + PCIE_LINK_STATUS_REG) & - PCIE_CTRL_LINKUP), mdelay(1))) { - val = read32p(ctrl->base + PCIE_LTSSM_STATUS_REG); - ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ? - "Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)]; - printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n", - __func__, ltssm_state); - return -1; - } - - printk(BIOS_INFO, "%s: PCIe link up success (%ld tries)\n", __func__, - tries); - - return 0; + return (void *)(pcie_ctrl->base + PCIE_CFG_OFFSET_ADDR); } static int mtk_pcie_set_trans_window(struct device *dev, uintptr_t table, @@ -210,29 +164,31 @@ void mtk_pcie_domain_read_resources(struct device *dev) { - struct mtk_pcie_controller *ctrl = dev->chip_info; + const mtk_soc_config_t *config = config_of(dev); + const struct mtk_pcie_config *conf = &config->pcie_config; mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(0, 0), - ctrl->mmio_res_io); + &conf->mmio_res_io); mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(1, 0), - ctrl->mmio_res_mem); + &conf->mmio_res_mem); } void mtk_pcie_domain_set_resources(struct device *dev) { - struct mtk_pcie_controller *ctrl = dev->chip_info; + const mtk_soc_config_t *config = config_of(dev); + const struct mtk_pcie_config *conf = &config->pcie_config; uintptr_t table; /* Initialize I/O space constraints. */ - table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG; - if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_io) < 0) + table = conf->base + PCIE_TRANS_TABLE_BASE_REG; + if (mtk_pcie_set_trans_window(dev, table, &conf->mmio_res_io) < 0) printk(BIOS_ERR, "%s: Failed to set IO window\n", __func__); /* Initialize memory resources constraints. */ - table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG + + table = conf->base + PCIE_TRANS_TABLE_BASE_REG + PCIE_ATR_TLB_SET_OFFSET; - if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_mem) < 0) + if (mtk_pcie_set_trans_window(dev, table, &conf->mmio_res_mem) < 0) printk(BIOS_ERR, "%s: Failed to set MEM window\n", __func__); pci_domain_set_resources(dev); @@ -240,10 +196,43 @@ void mtk_pcie_domain_enable(struct device *dev) { - mtk_pcie_get_hw_info(&pcie_ctrl); + const mtk_soc_config_t *config = config_of(dev); + const char *ltssm_state; + size_t tries = 0; + uint32_t val; - if (mtk_pcie_startup_port(&pcie_ctrl) < 0) + pcie_ctrl = &config->pcie_config; + + /* Set as RC mode */ + val = read32p(pcie_ctrl->base + PCIE_SETTING_REG); + val |= PCIE_RC_MODE; + write32p(pcie_ctrl->base + PCIE_SETTING_REG, val); + + /* Set class code */ + val = read32p(pcie_ctrl->base + PCIE_PCI_IDS_1); + val &= ~GENMASK(31, 8); + val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); + write32p(pcie_ctrl->base + PCIE_PCI_IDS_1, val); + + /* Mask all INTx interrupts */ + val = read32p(pcie_ctrl->base + PCIE_INT_ENABLE_REG); + val &= ~PCIE_INTX_ENABLE; + write32p(pcie_ctrl->base + PCIE_INT_ENABLE_REG, val); + + /* De-assert reset signals */ + mtk_pcie_reset(pcie_ctrl->base + PCIE_RST_CTRL_REG, false); + + if (!retry(100, + (tries++, read32p(pcie_ctrl->base + PCIE_LINK_STATUS_REG) & + PCIE_CTRL_LINKUP), mdelay(1))) { + val = read32p(pcie_ctrl->base + PCIE_LTSSM_STATUS_REG); + ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ? + "Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)]; + printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n", + __func__, ltssm_state); return; + } - dev->chip_info = &pcie_ctrl; + printk(BIOS_INFO, "%s: PCIe link up success (%ld tries)\n", __func__, + tries); } diff --git a/src/soc/mediatek/mt8195/chip.h b/src/soc/mediatek/mt8195/chip.h new file mode 100644 index 0000000..7cc4d19 --- /dev/null +++ b/src/soc/mediatek/mt8195/chip.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_CHIP_H +#define SOC_MEDIATEK_CHIP_H + +#include <soc/pcie_common.h> + +struct soc_mediatek_mt8195_config { + struct mtk_pcie_config pcie_config; +}; + +typedef struct soc_mediatek_mt8195_config mtk_soc_config_t; + +#endif /* SOC_MEDIATEK_CHIP_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h index 0978531..21a6668 100644 --- a/src/soc/mediatek/mt8195/include/soc/pcie.h +++ b/src/soc/mediatek/mt8195/include/soc/pcie.h @@ -5,7 +5,7 @@ #include <soc/pcie_common.h> +void mtk_pcie_reset(uintptr_t reg, bool enable); void mtk_pcie_pre_init(void); -void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl); #endif diff --git a/src/soc/mediatek/mt8195/include/soc/soc_chip.h b/src/soc/mediatek/mt8195/include/soc/soc_chip.h new file mode 100644 index 0000000..6b3c354 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_SOC_CHIP_H +#define SOC_MEDIATEK_SOC_CHIP_H + +#include "../../chip.h" + +#endif /* SOC_MEDIATEK_SOC_CHIP_H */ diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index 8a1fca4..1a17c6c 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -19,23 +19,6 @@ #define PCIE_BRG_RSTB BIT(2) #define PCIE_PE_RSTB BIT(3) - -/* MMIO range (64MB): 0x20000000 ~ 0x24000000 */ -/* Some devices still need io ranges, reserve 16MB for compatibility */ -static const struct mtk_pcie_mmio_res pcie_mmio_res_io = { - .cpu_addr = 0x20000000, - .pci_addr = 0x20000000, - .size = 16 * MiB, - .type = IORESOURCE_IO, -}; - -static const struct mtk_pcie_mmio_res pcie_mmio_res_mem = { - .cpu_addr = 0x21000000, - .pci_addr = 0x21000000, - .size = 48 * MiB, - .type = IORESOURCE_MEM, -}; - struct pad_func { gpio_t gpio; u8 func; @@ -67,7 +50,7 @@ } } -static void mtk_pcie_reset(uintptr_t reg, bool enable) +void mtk_pcie_reset(uintptr_t reg, bool enable) { uint32_t val; @@ -90,11 +73,3 @@ /* Assert all reset signals at early stage */ mtk_pcie_reset(PCIE_RST_CTRL_REG, true); } - -void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl) -{ - ctrl->base = PCIE_REG_BASE_PORT0; - ctrl->mmio_res_io = &pcie_mmio_res_io; - ctrl->mmio_res_mem = &pcie_mmio_res_mem; - ctrl->reset = &mtk_pcie_reset; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/62791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Gerrit-Change-Number: 62791 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: driver/intel/usb4/retimer: Change loglevel prefix
by Tim Wawrzynczak (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Subrata Banik, Chen Wisley, Wisley Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62822 ) Change subject: driver/intel/usb4/retimer: Change loglevel prefix ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/drivers/intel/usb4/retimer/retimer.c: https://review.coreboot.org/c/coreboot/+/62822/comment/8529d4b5_4344b01d PS1, Line 361: BIOS_INFO > BIOS_WARN […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I508ec7662e078893f944edb3d68364c57d5c5a73 Gerrit-Change-Number: 62822 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 16:50:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Remove IOM Mctp command from TCSS ASL
by Tim Wawrzynczak (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Shobhit Srivastava, Subrata Banik, Maulik V Vaghela, Sridhar Siricilla, Kane Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62861 ) Change subject: soc/intel/adl: Remove IOM Mctp command from TCSS ASL ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62861/comment/8a286093_53acc0b0 PS2, Line 14: Due to change in hardware sequence maybe mention like `We discovered that due to a change in the hardware sequence...` https://review.coreboot.org/c/coreboot/+/62861/comment/7a9ee1b5_a66616e9 PS2, Line 26: MAULIK V VAGHELA is your name in git config still set to all caps? 😄 File src/soc/intel/alderlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/62861/comment/8c2e038a_faa6aa3f PS2, Line 694: /* : * If the TCSS Deven is cleared by BIOS Mailbox request, then : * restore to previously saved value of TCSS DEVNE. : */ : Local0 = 0 : While (\_SB.PCI0.TXHC.VDID == 0xFFFFFFFF) { : If (DSGS () == 1) { : DSCR (0) : } : Local0++ : If (Local0 == 5) { : Printf("pCode mailbox command failed.") : Break : } : } Is this part still necessary too? I don't see the reference code doing this. https://review.coreboot.org/c/coreboot/+/62861/comment/e7e82603_d0feb82d PS2, Line 725: /* : * If the TCSS Deven in normal state, then Save current TCSS DEVEN value and : * clear it. : */ : Local0 = 0 : While (\_SB.PCI0.TXHC.VDID != 0xFFFFFFFF) { : If (DSGS () == 0) { : DSCR (1) : } : Local0++ : If (Local0 == 5) { : Printf("pCode mailbox command failed.") : Break : } : } Is this part still necessary too? I don't see the reference code doing this. -- To view, visit https://review.coreboot.org/c/coreboot/+/62861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb Gerrit-Change-Number: 62861 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 16:46:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Remove the allocator workaround
by build bot (Jenkins) (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Patrick Rudolph, Tim Chu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62353 ) Change subject: soc/intel/xeon_sp: Remove the allocator workaround ...................................................................... Patch Set 6: Verified+1 (1 comment) File src/soc/intel/xeon_sp/chip_common.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144131): https://review.coreboot.org/c/coreboot/+/62353/comment/7b3883b9_4129af4c PS6, Line 63: res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/62353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedca35cca8350eb53b5be04c42474d2b4c9d347f Gerrit-Change-Number: 62353 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 16:45:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: update overridetree
by Tim Wawrzynczak (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: YH Lin, Subrata Banik, Paul Menzel, Zhuohao Lee, EricR Lai, Raihow Shi, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62852 ) Change subject: mb/google/brask/variants/moli: update overridetree ...................................................................... Patch Set 32: (1 comment) Patchset: PS32: Is there a reason this can't be squashed into CB:62321 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/62852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If878362fe8b2e1d3397ca099477bb85bd4dee926 Gerrit-Change-Number: 62852 Gerrit-PatchSet: 32 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 16 Mar 2022 16:38:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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