coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/skyrim: Enable tis_plat_irq_status
by Raul Rangel (Code Review) 16 Mar '22

16 Mar '22

Raul Rangel has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/62873 ) Change subject: mb/google/skyrim: Enable tis_plat_irq_status ...................................................................... mb/google/skyrim: Enable tis_plat_irq_status This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:224618411 TEST=Compile skyrim Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5add694506ad089adcc8961f101bf507bc39a522 --- M src/mainboard/google/skyrim/variants/baseboard/Makefile.inc M src/mainboard/google/skyrim/variants/baseboard/gpio.c A src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c 3 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/62873/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5add694506ad089adcc8961f101bf507bc39a522 Gerrit-Change-Number: 62873 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/skyrim: Enable tis_plat_irq_status
by Raul Rangel (Code Review) 16 Mar '22

16 Mar '22

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62873 ) Change subject: mb/google/skyrim: Enable tis_plat_irq_status ...................................................................... mb/google/skyrim: Enable tis_plat_irq_status This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:224618411 TEST=Compile skyrim Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5add694506ad089adcc8961f101bf507bc39a522 --- M src/mainboard/google/skyrim/variants/baseboard/Makefile.inc M src/mainboard/google/skyrim/variants/baseboard/gpio.c 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/62873/1 diff --git a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc index dc1c1fe..7706e50 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc @@ -1,7 +1,11 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += tpm_tis.c ramstage-y += gpio.c +ramstage-y += tpm_tis.c + +verstage-y += tpm_tis.c smm-y += gpio.c diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index f095651..204ddf6 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -39,7 +39,7 @@ /* SOC_SAR_INT_L */ PAD_SCI(GPIO_17, PULL_NONE, EDGE_LOW), /* GSC_SOC_INT_L */ - PAD_GPI(GPIO_18, PULL_NONE), + PAD_INT(GPIO_18, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* I2C3_SCL */ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5add694506ad089adcc8961f101bf507bc39a522 Gerrit-Change-Number: 62873 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Jon Murphy, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62872 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Add counter initializers ...................................................................... soc/amd/cezanne: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3 --- M src/soc/amd/cezanne/fsp_m_params.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62872/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3 Gerrit-Change-Number: 62872 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Jon Murphy, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62871 to look at the new patch set (#2). Change subject: soc/amd/picasso: Add counter initializers ...................................................................... soc/amd/picasso: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3 --- M src/soc/amd/picasso/fsp_s_params.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62871/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3 Gerrit-Change-Number: 62871 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/sabrina: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62863 ) Change subject: soc/amd/sabrina: Add counter initializers ...................................................................... Patch Set 7: (1 comment) Patchset: PS6: > please also fix this for the earlier socs. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d Gerrit-Change-Number: 62863 Gerrit-PatchSet: 7 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 17:05:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62872 ) Change subject: soc/amd/cezanne: Add counter initializers ...................................................................... soc/amd/cezanne: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3 --- M src/soc/amd/cezanne/fsp_m_params.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62872/1 diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 92debe3..8c9e5a1 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -45,10 +45,10 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) { - const fsp_dxio_descriptor *fsp_dxio; - const fsp_ddi_descriptor *fsp_ddi; - size_t num_dxio; - size_t num_ddi; + const fsp_dxio_descriptor *fsp_dxio = NULL; + const fsp_ddi_descriptor *fsp_ddi = NULL; + size_t num_dxio = 0; + size_t num_ddi = 0; mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, &fsp_ddi, &num_ddi); -- To view, visit https://review.coreboot.org/c/coreboot/+/62872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3 Gerrit-Change-Number: 62872 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/sabrina: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Jon Murphy. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62863 to look at the new patch set (#7). Change subject: soc/amd/sabrina: Add counter initializers ...................................................................... soc/amd/sabrina: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d --- M src/soc/amd/sabrina/fsp_m_params.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/62863/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d Gerrit-Change-Number: 62863 Gerrit-PatchSet: 7 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62871 ) Change subject: soc/amd/picasso: Add counter initializers ...................................................................... soc/amd/picasso: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3 --- M src/soc/amd/picasso/fsp_s_params.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62871/1 diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c index af7de37..2e10555 100644 --- a/src/soc/amd/picasso/fsp_s_params.c +++ b/src/soc/amd/picasso/fsp_s_params.c @@ -92,10 +92,10 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) { - const fsp_dxio_descriptor *fsp_dxio; - const fsp_ddi_descriptor *fsp_ddi; - size_t num_dxio; - size_t num_ddi; + const fsp_dxio_descriptor *fsp_dxio = NULL; + const fsp_ddi_descriptor *fsp_ddi = NULL; + size_t num_dxio = 0; + size_t num_ddi = 0; mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, &fsp_ddi, &num_ddi); -- To view, visit https://review.coreboot.org/c/coreboot/+/62871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3 Gerrit-Change-Number: 62871 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK HACK required changes for rebase HACK HACK
by mturney mturney (Code Review) 16 Mar '22

16 Mar '22

mturney mturney has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51653 ) Change subject: HACK HACK required changes for rebase HACK HACK ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/51653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28040f295a155246a0790c4eb22626371b2667b0 Gerrit-Change-Number: 51653 Gerrit-PatchSet: 33 Gerrit-Owner: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge
by Felix Held (Code Review) 16 Mar '22

16 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62631 ) Change subject: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge ...................................................................... mb/google/brya/var/kinox: Enable PCIe-eMMC bridge Enable PCIe-eMMC bridge for Kinox. BUG=b:218786363, b:211176722 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62631 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kinox/gpio.c M src/mainboard/google/brya/variants/kinox/overridetree.cb 2 files changed, 18 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kinox/gpio.c b/src/mainboard/google/brya/variants/kinox/gpio.c index 0fbfee0..fa63c1d 100644 --- a/src/mainboard/google/brya/variants/kinox/gpio.c +++ b/src/mainboard/google/brya/variants/kinox/gpio.c @@ -41,7 +41,7 @@ /* D17 : UART1_RXD ==> NC */ PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> EMMC_PE_RST_L */ - PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), + PAD_CFG_GPO(GPP_D18, 1, DEEP), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ /* E4 : SATA_DEVSLP0 ==> USB_A1_RT_RST_ODL */ @@ -93,6 +93,8 @@ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* D18 : UART1_TXD ==> EMMC_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F14 : GSXDIN ==> EN_PP3300_SSD */ @@ -107,7 +109,7 @@ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + /* H13 : I2C7_SCL ==> EN_PP3300_EMMC */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* CPU PCIe VGPIO for PEG60 */ diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index a4050ee..96e621e 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -187,6 +187,20 @@ device generic 0 alias dptf_policy on end end end + device ref pcie_rp6 on + # Enable PCIe-to-eMMC bridge PCIE 6 using clk 1 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "1" + device generic 0 alias emmc_rtd3 on end + end + end # BH799BBLN device ref pcie_rp7 on chip drivers/net register "customized_leds" = "0x05af" 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Gerrit-Change-Number: 62631 Gerrit-PatchSet: 6 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022