coreboot-gerrit November 2022

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[M] Change in coreboot[master]: mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table
by Eric Lai (Code Review) 05 Nov '22

05 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69177 ) Change subject: mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table ...................................................................... mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table Rename so table more indicative of when GPIOs are set, and so it can be used for more than just setting PCIe GPIOs. Will be used to set touchscreen GPIOs as part of power sequencing in a subsequent commit. Rename all variant tables and getter functions to match. This mirrors the changes made for skyrim in CB:67810 Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69177 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/romstage.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/variants/dewatt/gpio.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/gpio.c 6 files changed, 45 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c index 0b7649b..571eb44 100644 --- a/src/mainboard/google/guybrush/romstage.c +++ b/src/mainboard/google/guybrush/romstage.c @@ -8,9 +8,9 @@ size_t base_num_gpios, override_num_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios; - /* Initialize PCIe reset. */ - base_gpios = baseboard_pcie_gpio_table(&base_num_gpios); - override_gpios = variant_pcie_override_gpio_table(&override_num_gpios); + /* Initialize PCIe reset and other romstage GPIOs */ + base_gpios = baseboard_romstage_gpio_table(&base_num_gpios); + override_gpios = variant_romstage_override_gpio_table(&override_num_gpios); gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, override_num_gpios); diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 1ee70da..beb654f 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -268,7 +268,7 @@ }; /* PCIE_RST needs to be brought high before FSP-M runs */ -static const struct soc_amd_gpio pcie_gpio_table[] = { +static const struct soc_amd_gpio romstage_gpio_table[] = { /* Deassert all AUX_RESET lines & PCIE_RST */ /* Unused */ PAD_NC(GPIO_5), @@ -286,10 +286,10 @@ PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), }; -const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size) +const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) { - *size = ARRAY_SIZE(pcie_gpio_table); - return pcie_gpio_table; + *size = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size) @@ -322,7 +322,7 @@ return NULL; } -const struct soc_amd_gpio * __weak variant_pcie_override_gpio_table(size_t *size) +const struct soc_amd_gpio * __weak variant_romstage_override_gpio_table(size_t *size) { *size = 0; return NULL; diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 9a57c41..24c03b0 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -21,7 +21,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size); const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size); -const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size); /* This function provides early GPIO init in early bootblock or psp. */ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); @@ -30,7 +30,7 @@ const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size); /* This function provides GPIO settings before PCIe enumeration. */ -const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size); +const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size); /* This function provides GPIO settings for eSPI bus. */ const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); diff --git a/src/mainboard/google/guybrush/variants/dewatt/gpio.c b/src/mainboard/google/guybrush/variants/dewatt/gpio.c index 10486351..571cbb4 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/gpio.c +++ b/src/mainboard/google/guybrush/variants/dewatt/gpio.c @@ -53,7 +53,7 @@ }; /* This table is used by guybrush variant */ -static const struct soc_amd_gpio override_pcie_gpio_table[] = { +static const struct soc_amd_gpio override_romstage_gpio_table[] = { /* Unused TP195*/ PAD_NC(GPIO_18), /* Unused TP217*/ @@ -78,10 +78,10 @@ return override_early_gpio_table; } -const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size) { - *size = ARRAY_SIZE(override_pcie_gpio_table); - return override_pcie_gpio_table; + *size = ARRAY_SIZE(override_romstage_gpio_table); + return override_romstage_gpio_table; } const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size) diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index f3ed09f..dcbda20 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -48,7 +48,7 @@ }; /* This table is used by guybrush variant with board version < 2. */ -static const struct soc_amd_gpio bid1_pcie_gpio_table[] = { +static const struct soc_amd_gpio bid1_romstage_gpio_table[] = { /* SD_AUX_RESET_L */ PAD_GPO(GPIO_70, HIGH), }; @@ -87,13 +87,13 @@ return override_early_gpio_table; } -const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); *size = 0; if (board_version < 2) { - *size = ARRAY_SIZE(bid1_pcie_gpio_table); - return bid1_pcie_gpio_table; + *size = ARRAY_SIZE(bid1_romstage_gpio_table); + return bid1_romstage_gpio_table; } return NULL; diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 0fdedbf..c9f637c 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -47,7 +47,7 @@ PAD_GPO(GPIO_31, LOW), }; -static const struct soc_amd_gpio override_pcie_gpio_table[] = { +static const struct soc_amd_gpio override_romstage_gpio_table[] = { PAD_NC(GPIO_18), }; @@ -91,10 +91,10 @@ return override_early_gpio_table; } -const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size) { - *size = ARRAY_SIZE(override_pcie_gpio_table); - return override_pcie_gpio_table; + *size = ARRAY_SIZE(override_romstage_gpio_table); + return override_romstage_gpio_table; } const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/69177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e Gerrit-Change-Number: 69177 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/guybrush: rename baseboard GPIO table getter for clarity
by Eric Lai (Code Review) 05 Nov '22

05 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69176 ) Change subject: mb/google/guybrush: rename baseboard GPIO table getter for clarity ...................................................................... mb/google/guybrush: rename baseboard GPIO table getter for clarity Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69176 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/romstage.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h 3 files changed, 26 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c index 23e7853..0b7649b 100644 --- a/src/mainboard/google/guybrush/romstage.c +++ b/src/mainboard/google/guybrush/romstage.c @@ -9,7 +9,7 @@ const struct soc_amd_gpio *base_gpios, *override_gpios; /* Initialize PCIe reset. */ - base_gpios = variant_pcie_gpio_table(&base_num_gpios); + base_gpios = baseboard_pcie_gpio_table(&base_num_gpios); override_gpios = variant_pcie_override_gpio_table(&override_num_gpios); gpio_configure_pads_with_override(base_gpios, base_num_gpios, diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 8554c4c..1ee70da 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -286,7 +286,7 @@ PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), }; -const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size) +const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size) { *size = ARRAY_SIZE(pcie_gpio_table); return pcie_gpio_table; diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index bf69443..9a57c41 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -30,7 +30,7 @@ const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size); /* This function provides GPIO settings before PCIe enumeration. */ -const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size); +const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size); /* This function provides GPIO settings for eSPI bus. */ const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); -- To view, visit https://review.coreboot.org/c/coreboot/+/69176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1 Gerrit-Change-Number: 69176 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: lib: Add LPDDR5x DRAM type
by Eric Lai (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Subrata Banik, Kapil Porwal, Ivy Jian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69226 ) Change subject: lib: Add LPDDR5x DRAM type ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If620cf51133ca295fd3f1cbecbb472beb337b9fc Gerrit-Change-Number: 69226 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 12:12:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vboot: Introduce handy vboot reboot functions
by Eric Lai (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Jakub Czapiga. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69208 ) Change subject: vboot: Introduce handy vboot reboot functions ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Patchset: PS1: I like the refactor, nice. File src/security/vboot/vboot_common.c: https://review.coreboot.org/c/coreboot/+/69208/comment/b8ac6556_da425fbf PS1, Line 14: if (!verification_should_run() && !(ENV_ROMSTAGE && CONFIG(VBOOT_EARLY_EC_SYNC)) Is this block belong to the next patch? File src/security/vboot/vboot_logic.c: https://review.coreboot.org/c/coreboot/+/69208/comment/0ee43278_0cb7afae PS1, Line 354: vboot_save_data(ctx); Any side effect if we save twice? Should be fine I think. -- To view, visit https://review.coreboot.org/c/coreboot/+/69208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5 Gerrit-Change-Number: 69208 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 12:11:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: HACK: Add ramstage sources to bootblock
by build bot (Jenkins) (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Jason Glenesk, Martin L Roth, Matt DeVillier, Julius Werner, Fred Reitberger, Yu-Ping Wu, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69240 ) Change subject: HACK: Add ramstage sources to bootblock ...................................................................... Patch Set 3: (2 comments) File src/include/rules.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162577): https://review.coreboot.org/c/coreboot/+/69240/comment/fe3668f1_b3f5936b PS3, Line 282: #define ENV_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) || ENV_BOOTBLOCK Macros with complex values should be enclosed in parentheses File src/lib/hardwaremain.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162577): https://review.coreboot.org/c/coreboot/+/69240/comment/6fe69074_efb00ac6 PS3, Line 444: /* init_timer(); */ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/69240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ac96ada466d4410c80ea53f7d4ff05948e3c566 Gerrit-Change-Number: 69240 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 05 Nov 2022 11:48:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: link Agesa into bootblock
by build bot (Jenkins) (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55070 ) Change subject: link Agesa into bootblock ...................................................................... Patch Set 38: Verified+1 (1 comment) File src/drivers/amd/agesa/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162575): https://review.coreboot.org/c/coreboot/+/55070/comment/b7f15b45_03a30f20 PS38, Line 47: void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); function definition argument 'void' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/55070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4c71b9c9a245e07d713839fb3628cbfc0dc3457 Gerrit-Change-Number: 55070 Gerrit-PatchSet: 38 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 11:47:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: Allow to build romstage sources inside the bootblock
by Arthur Heymans (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Branden Waldner, Martin L Roth, Jakub Czapiga, ron minnich, Paul Menzel, Stefan Reinauer, Christian Walter, Julius Werner, Angel Pons, Keith Hui, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Philipp Hug, Jakub Czapiga, Frans Hendriks, ron minnich, Stefan Reinauer, Subrata Banik, Julius Werner, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Piotr Król, Erik van den Bogaert, Jason Glenesk, Michał Żygowski, Martin L Roth, Marshall Dawson, Christian Walter, Yu-Ping Wu, ron minnich, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55068 to look at the new patch set (#33). Change subject: Allow to build romstage sources inside the bootblock ...................................................................... Allow to build romstage sources inside the bootblock Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/Kconfig M src/arch/arm64/romstage.c M src/arch/x86/Makefile.inc M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/arch/x86/memcpy.c M src/arch/x86/memlayout.ld M src/arch/x86/memmove.c M src/arch/x86/memset.c M src/commonlib/storage/sdhci.c M src/console/Kconfig M src/console/console.c M src/console/init.c M src/drivers/net/ne2k.c M src/drivers/siemens/nc_fpga/nc_fpga_early.c M src/drivers/usb/ehci_debug.c M src/drivers/vpd/vpd.c M src/include/cbmem.h M src/include/console/cbmem_console.h M src/include/console/console.h M src/include/console/ne2k.h M src/include/console/qemu_debugcon.h M src/include/console/spkmodem.h M src/include/console/system76_ec.h M src/include/console/uart.h M src/include/console/usb.h M src/include/memlayout.h M src/include/rules.h M src/include/symbols.h M src/include/timestamp.h M src/lib/asan.c M src/lib/cbfs.c M src/lib/prog_loaders.c M src/mainboard/emulation/qemu-armv7/romstage.c M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/poppy/variants/nautilus/sku.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/ti/beaglebone/romstage.c M src/security/tpm/tspi/log.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/common.c M src/security/vboot/misc.h M src/soc/intel/common/block/pmc/pmclib.c M src/vendorcode/eltan/security/verified_boot/vboot_check.c M tests/lib/imd_cbmem-test.c 53 files changed, 158 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/55068/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/55068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Gerrit-Change-Number: 55068 Gerrit-PatchSet: 33 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)chromium.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: ron minnich <rminnich(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: HACK: Add ramstage sources to bootblock
by build bot (Jenkins) (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Jason Glenesk, Martin L Roth, Matt DeVillier, Julius Werner, Fred Reitberger, Yu-Ping Wu, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69240 ) Change subject: HACK: Add ramstage sources to bootblock ...................................................................... Patch Set 2: (2 comments) File src/include/rules.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162571): https://review.coreboot.org/c/coreboot/+/69240/comment/da4b9926_577e3b00 PS2, Line 282: #define ENV_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) || ENV_BOOTBLOCK Macros with complex values should be enclosed in parentheses File src/lib/hardwaremain.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162571): https://review.coreboot.org/c/coreboot/+/69240/comment/070feae9_5b9b8cdd PS2, Line 444: /* init_timer(); */ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/69240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ac96ada466d4410c80ea53f7d4ff05948e3c566 Gerrit-Change-Number: 69240 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 05 Nov 2022 11:46:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: link Agesa into bootblock
by build bot (Jenkins) (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55070 ) Change subject: link Agesa into bootblock ...................................................................... Patch Set 37: Verified+1 (1 comment) File src/drivers/amd/agesa/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162569): https://review.coreboot.org/c/coreboot/+/55070/comment/70a7ab0f_01359275 PS37, Line 47: void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); function definition argument 'void' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/55070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4c71b9c9a245e07d713839fb3628cbfc0dc3457 Gerrit-Change-Number: 55070 Gerrit-PatchSet: 37 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 11:45:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function
by Johnny Lin (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Marc Jones, Angel Pons. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69144 ) Change subject: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > ewww. That seems like an issue that should be brought to the attention of gerrit developers. […] Sorry to cause this chaos, I should have marked the depending changes WIP to avoid this. Besides manual operations to avoid this, if Jenkins could detect and put out warnings when the changes depend on any private change, something like not building it would be better. -- To view, visit https://review.coreboot.org/c/coreboot/+/69144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Gerrit-Change-Number: 69144 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 11:45:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit November 2022