coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/amd/common/block/noncar: Merge romstage into bootblock
by Arthur Heymans (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64950 to look at the new patch set (#13). Change subject: soc/amd/common/block/noncar: Merge romstage into bootblock ...................................................................... soc/amd/common/block/noncar: Merge romstage into bootblock Separate stages for bootblock & romstage does not make a lot of sense on these systems as they start executing code in DRAM. Change-Id: I7bd5affdb7f40cbd3bd4e599c3a5cb79984fea68 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/64950/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/64950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bd5affdb7f40cbd3bd4e599c3a5cb79984fea68 Gerrit-Change-Number: 64950 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: Allow to build romstage sources inside the bootblock
by Arthur Heymans (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Branden Waldner, Martin L Roth, Jakub Czapiga, ron minnich, Paul Menzel, Stefan Reinauer, Angel Pons, Arthur Heymans, Keith Hui, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Philipp Hug, Jakub Czapiga, Frans Hendriks, ron minnich, Stefan Reinauer, Subrata Banik, Julius Werner, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Piotr Król, Erik van den Bogaert, Jason Glenesk, Michał Żygowski, Martin L Roth, Marshall Dawson, Yu-Ping Wu, ron minnich, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55068 to look at the new patch set (#31). Change subject: Allow to build romstage sources inside the bootblock ...................................................................... Allow to build romstage sources inside the bootblock Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/Kconfig M src/arch/arm64/romstage.c M src/arch/x86/Makefile.inc M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/arch/x86/memcpy.c M src/arch/x86/memlayout.ld M src/arch/x86/memmove.c M src/arch/x86/memset.c M src/commonlib/storage/sdhci.c M src/console/Kconfig M src/console/console.c M src/console/init.c M src/drivers/net/ne2k.c M src/drivers/siemens/nc_fpga/nc_fpga_early.c M src/drivers/usb/ehci_debug.c M src/drivers/vpd/vpd.c M src/include/cbmem.h M src/include/console/cbmem_console.h M src/include/console/console.h M src/include/console/ne2k.h M src/include/console/qemu_debugcon.h M src/include/console/spkmodem.h M src/include/console/system76_ec.h M src/include/console/uart.h M src/include/console/usb.h M src/include/memlayout.h M src/include/rules.h M src/include/symbols.h M src/include/timestamp.h M src/lib/asan.c M src/lib/cbfs.c M src/lib/prog_loaders.c M src/mainboard/emulation/qemu-armv7/romstage.c M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/poppy/variants/nautilus/sku.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/ti/beaglebone/romstage.c M src/security/tpm/tspi/log.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/common.c M src/security/vboot/misc.h M src/soc/intel/common/block/pmc/pmclib.c M src/vendorcode/eltan/security/verified_boot/vboot_check.c M tests/lib/imd_cbmem-test.c 53 files changed, 151 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/55068/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/55068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Gerrit-Change-Number: 55068 Gerrit-PatchSet: 31 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)chromium.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: ron minnich <rminnich(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SB
by build bot (Jenkins) (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69041 ) Change subject: soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SB ...................................................................... Patch Set 5: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162556): https://review.coreboot.org/c/coreboot/+/69041/comment/8bdef7be_c8678b78 PS5, Line 6: Possible long commit subject (prefer a maximum 65 characters) -- To view, visit https://review.coreboot.org/c/coreboot/+/69041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Gerrit-Change-Number: 69041 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 10:59:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SB
by Subrata Banik (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Arthur Heymans, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69041 to look at the new patch set (#4). Change subject: soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SB ...................................................................... soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SB This patch uses index 0x10 for IOE P2SB memory resource allocation instead of static 0. Additionally, switches to `mmio_resource` from `mmio_resource_kb`. TEST=Able to build and boot Google/Rex and observed log as below. Without the code change: [SPEW ] PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 0 With the code change: [SPEW ] PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 --- M src/soc/intel/meteorlake/p2sb.c 1 file changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/69041/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Gerrit-Change-Number: 69041 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Use index 0x10 instead of 0 for P2SB
by Subrata Banik (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Arthur Heymans, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69041 to look at the new patch set (#3). Change subject: soc/intel/meteorlake: Use index 0x10 instead of 0 for P2SB ...................................................................... soc/intel/meteorlake: Use index 0x10 instead of 0 for P2SB This patch uses index 0x10 for P2SB memory resource allocation instead of static 0. TEST=Able to build and boot Google/Rex and observed log as below. Without the code change: [SPEW ] PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 0 With the code change: [SPEW ] PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 --- M src/soc/intel/meteorlake/p2sb.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/69041/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Gerrit-Change-Number: 69041 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Use index 0x10 instead of 0 for P2SB
by build bot (Jenkins) (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69041 ) Change subject: soc/intel/meteorlake: Use index 0x10 instead of 0 for P2SB ...................................................................... Patch Set 2: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162555): https://review.coreboot.org/c/coreboot/+/69041/comment/89d77c62_035172ba PS2, Line 6: Possible long commit subject (prefer a maximum 65 characters) -- To view, visit https://review.coreboot.org/c/coreboot/+/69041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Gerrit-Change-Number: 69041 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 10:52:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cannonlake: Fix GPIO reset mapping
by Subrata Banik (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Tim Crawford, Matt DeVillier, Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69214 ) Change subject: soc/intel/cannonlake: Fix GPIO reset mapping ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib586c987f768ddff31b053f4c108a8526326a7dc Gerrit-Change-Number: 69214 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 09:59:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: configs: Rename saved configs as config.vendor_board.description
by Angel Pons (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69213 ) Change subject: configs: Rename saved configs as config.vendor_board.description ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69213/comment/c7d17c13_ea49c69a PS2, Line 10: for the config to be found by the build system. Several of the configs probably have the wrong name because the boards got folded into variants afterwards -- To view, visit https://review.coreboot.org/c/coreboot/+/69213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008610ff87b3dd6c4b6c6b04fbdbc30a18ba776b Gerrit-Change-Number: 69213 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 09:57:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: lib/ramtest.c: Update ram failure post code
by Angel Pons (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Martin L Roth, Matt DeVillier, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69202 ) Change subject: lib/ramtest.c: Update ram failure post code ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File src/lib/ramtest.c: https://review.coreboot.org/c/coreboot/+/69202/comment/a31905e0_e97ace8f PS1, Line 113: POST_RAM_FAILURE > maybe just for the 2nd one since this is nodie() Right, nothing to do here. https://review.coreboot.org/c/coreboot/+/69202/comment/74dd310d_ec2eb8ce PS1, Line 203: POST_RAM_FAILURE > same as above Yes, we should use `die_with_post_code()` -- To view, visit https://review.coreboot.org/c/coreboot/+/69202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21ef196e48ff37ffe320b575d6de66b43997e7eb Gerrit-Change-Number: 69202 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 09:53:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device & commonlib: Update pci_scan_bus postcodes
by Angel Pons (Code Review) 05 Nov '22

05 Nov '22

Attention is currently required from: Felix Singer, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69201 ) Change subject: device & commonlib: Update pci_scan_bus postcodes ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69201/comment/63b0c207_cefd6dcc PS2, Line 18: code. Those postcodes should be adjusted to avoid conflicting. Could we shift the PCI bus scan postcodes instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/69201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3 Gerrit-Change-Number: 69201 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sat, 05 Nov 2022 09:52:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022