coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/intel/alderlake: Set PL1 Time to Intel default 56s for certain CPUs
by Michał Żygowski (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69217 ) Change subject: soc/intel/alderlake: Set PL1 Time to Intel default 56s for certain CPUs ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69217/comment/60a292db_3a9c6f12 PS2, Line 12: > Please add a reference to the data sheet. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02c56b981d956bef58ae90f7f317a231416a2e54 Gerrit-Change-Number: 69217 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Nov 2022 12:33:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake: Set PL1 Time to Intel default 56s for certain CPUs
by Michał Żygowski (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Michał Żygowski, Subrata Banik. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69217 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Set PL1 Time to Intel default 56s for certain CPUs ...................................................................... soc/intel/alderlake: Set PL1 Time to Intel default 56s for certain CPUs Mobile SKUs with TDP equal to 45W should have PL1 Time equal 56 seconds. Desktop ADL-S SKUs with TDP 125W or higher also default to 56 seconds of PL1 Time. All SBGA SKUs also have 56s PL1 Time, however we lack CPUIDs/PCI IDs and general support for those CPUs. Based on public 12th Generation Intel Core Processors Datasheet Volume 1 Rev. 009 Section 4.2.2. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I02c56b981d956bef58ae90f7f317a231416a2e54 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/systemagent.c M src/soc/intel/common/block/include/intelblocks/power_limit.h 3 files changed, 58 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/69217/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02c56b981d956bef58ae90f7f317a231416a2e54 Gerrit-Change-Number: 69217 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: arch/x86 & commonlib: Add macros for postcodes used in x86/tables
by Fred Reitberger (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Martin L Roth. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69200 ) Change subject: arch/x86 & commonlib: Add macros for postcodes used in x86/tables ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f Gerrit-Change-Number: 69200 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 12:25:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/include/gpio_defs.h: Add comment for accuracy
by Fred Reitberger (Code Review) 07 Nov '22

07 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69209 ) Change subject: soc/amd/common/include/gpio_defs.h: Add comment for accuracy ...................................................................... soc/amd/common/include/gpio_defs.h: Add comment for accuracy The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times slightly. Time PCO Others 1mS 0.915mS 1.220mS 2mS 2.013mS 2.684mS Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 187be51..718a45c 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -113,6 +113,7 @@ #define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT) #define GPIO_TIMEBASE_61uS 0 +/* The next value is only 183uS on Picasso. It is 244uS on Cezanne and later SoCs */ #define GPIO_TIMEBASE_183uS (1 << 4) #define GPIO_TIMEBASE_15560uS (1 << 7) #define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | GPIO_TIMEBASE_15560uS) -- To view, visit https://review.coreboot.org/c/coreboot/+/69209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 Gerrit-Change-Number: 69209 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cpu/haswell/*.c: Move chip_ops to cpu cluster
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Arthur Heymans, Raul Rangel, Tristan Corrick, Tim Wawrzynczak, Angel Pons, Jonathon Hall, Alexander Couzens, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/haswell/*.c: Move chip_ops to cpu cluster ...................................................................... Patch Set 6: (1 comment) File src/cpu/intel/haswell/haswell_init.c: https://review.coreboot.org/c/coreboot/+/59314/comment/27d07fb1_7855f25b PS2, Line 178: : struct cpu_vr_config vr_config = { 0 }; : msr_t msr; : : const struct cpu_intel_haswell_config *conf = config_of_lapic(); : vr_config = conf->vr_config; > Now that we always get the devicetree settings, this can be simplified: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Nov 2022 12:21:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
by build bot (Jenkins) (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69291 ) Change subject: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree ...................................................................... Patch Set 4: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162694): https://review.coreboot.org/c/coreboot/+/69291/comment/0f398e2f_91d7ebe5 PS4, Line 15: sed -i 's/domain 0 on/domain 0 on\n\t\tops sandybridge_pci_domain_ops/' \ Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Gerrit-Change-Number: 69291 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Mon, 07 Nov 2022 12:21:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Angel Pons, Alexander Couzens. Hello Stefan Ott, Angel Pons, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69297 to look at the new patch set (#4). Change subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm ...................................................................... cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/cpu/intel/model_1067x/chip.h M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/intel/speedstep.h M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p5ql-em/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/northbridge/intel/gm45/chip.h M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/x4x/northbridge.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c 34 files changed, 97 insertions(+), 127 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/69297/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Gerrit-Change-Number: 69297 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Angel Pons, Alexander Couzens. Hello Stefan Ott, Angel Pons, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69295 to look at the new patch set (#5). Change subject: nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree ...................................................................... nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p5ql-em/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/foxconn/g41s-k/variants/g41m/overridetree.cb M src/mainboard/foxconn/g41s-k/variants/g41s-k/overridetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/northbridge/intel/x4x/northbridge.c 23 files changed, 92 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/69295/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Gerrit-Change-Number: 69295 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Alexander Couzens, Evgeny Zinoviev. Hello Alexander Couzens, Evgeny Zinoviev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69294 to look at the new patch set (#5). Change subject: nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree ...................................................................... nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/t60/variants/t60/overridetree.cb M src/mainboard/lenovo/t60/variants/z61t/overridetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/northbridge/intel/i945/northbridge.c 13 files changed, 34 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/69294/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Gerrit-Change-Number: 69294 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Alexander Couzens. Hello Stefan Ott, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69293 to look at the new patch set (#5). Change subject: nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree ...................................................................... nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/northbridge/intel/gm45/northbridge.c 4 files changed, 18 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/69293/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Gerrit-Change-Number: 69293 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022