coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. Hello Angel Pons, Alexander Couzens, Evgeny Zinoviev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69291 to look at the new patch set (#6). Change subject: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree ...................................................................... nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree The following commands were used to do this: $ for tree in $(find -name *.cb -exec grep -l sandybridge {} \;); do \ sed -i 's/cpu_cluster 0 on/cpu_cluster 0 on\n\t\tops \ sandybridge_cpu_bus_ops/' $tree; done $ for tree in $(find -name *.cb -exec grep -l sandybridge {} \;); do \ sed -i 's/domain 0 on/domain 0 on\n\t\tops sandybridge_pci_domain_ops/' \ $tree; done Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb M src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/overridetree.cb M src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/overridetree.cb M src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/overridetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb M src/mainboard/hp/z220_series/variants/z220_sff_workstation/overridetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t520/variants/t520/overridetree.cb M src/mainboard/lenovo/t520/variants/w520/overridetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/t530/overridetree.cb M src/mainboard/lenovo/t530/variants/w530/overridetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/variants/x1/overridetree.cb M src/mainboard/lenovo/x220/variants/x220/overridetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/lenovo/x230/variants/x230/overridetree.cb M src/mainboard/lenovo/x230/variants/x230s/overridetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb M src/northbridge/intel/sandybridge/northbridge.c 81 files changed, 142 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/69291/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Gerrit-Change-Number: 69291 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/intel/model_2065x: Don't use a magic APIC
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#8) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59315 ) Change subject: cpu/intel/model_2065x: Don't use a magic APIC ...................................................................... cpu/intel/model_2065x: Don't use a magic APIC Move the chip configuration to the cpu cluster device. It looks like none of the devicetree were featuring a lapic 0xacac, nor was tcc_offset ever set, so this remains a NOP. Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_2065x/chip.h M src/cpu/intel/model_2065x/model_2065x_init.c M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb 5 files changed, 24 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/59315/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482 Gerrit-Change-Number: 59315 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Arthur Heymans, Alexander Couzens. Hello Stefan Ott, build bot (Jenkins), Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69290 to look at the new patch set (#6). Change subject: nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetree ...................................................................... nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetree Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/northbridge/intel/ironlake/northbridge.c 4 files changed, 18 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/69290/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f Gerrit-Change-Number: 69290 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/intel/haswell: Move chip_ops to cpu cluster
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Arthur Heymans, Raul Rangel, Tristan Corrick, Tim Wawrzynczak, Angel Pons, Jonathon Hall, Alexander Couzens, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#8) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/intel/haswell: Move chip_ops to cpu cluster ...................................................................... cpu/intel/haswell: Move chip_ops to cpu cluster The cpu cluster is always present and it's the proper device to contain the settings that need to be applied to all cpus. This makes it possible to remove the fake lapic from devicetrees. Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/msi/h81m-p33/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb M src/northbridge/intel/haswell/northbridge.c M src/soc/intel/broadwell/northbridge.c 21 files changed, 80 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59314/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common: Don't add more links
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69302 ) Change subject: soc/intel/common: Don't add more links ...................................................................... soc/intel/common: Don't add more links This is now properly handled in the common mp_init code. TESTED on prodrive/hermes. Change-Id: I8f4588094fa0c128963e5ee0ccd36402b588586b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/69302/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index d8ca0b3..f7a4593 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -142,10 +142,6 @@ struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); assert(dev != NULL); - /* In case link to APIC device is not found, create the one */ - if (!dev->link_list) - add_more_links(dev, 1); - soc_init_cpus(dev->link_list); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f4588094fa0c128963e5ee0ccd36402b588586b Gerrit-Change-Number: 69302 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cpu/haswell/*.c: Move chip_ops to cpu cluster
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

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[M] Change in coreboot[master]: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
by build bot (Jenkins) (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69291 ) Change subject: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree ...................................................................... Patch Set 5: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162707): https://review.coreboot.org/c/coreboot/+/69291/comment/67772637_c62dfb03 PS5, Line 15: sed -i 's/domain 0 on/domain 0 on\n\t\tops sandybridge_pci_domain_ops/' \ Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Gerrit-Change-Number: 69291 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Mon, 07 Nov 2022 12:36:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/haswell/*.c: Move chip_ops to cpu cluster
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Arthur Heymans, Raul Rangel, Tristan Corrick, Tim Wawrzynczak, Angel Pons, Jonathon Hall, Alexander Couzens, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/haswell/*.c: Move chip_ops to cpu cluster ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/auron/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59314/comment/e53fa3ba_cb8dee7c PS2, Line 20: device lapic 0xacac off end > Out of curiosity, I've compared static.c of the Asrock B85M Pro4 before and after changing the following: > > diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb > index 43a65f8197..e73a24bfcb 100644 > --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb > +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb > @@ -1,15 +1,15 @@ > +chip cpu/intel/haswell > + device cpu_cluster 0 on > + device lapic 0 on end > + device lapic 0xacac off end > + end > +end > + > chip northbridge/intel/haswell > > # This mainboard has VGA > register "gpu_ddi_e_connected" = "1" > > - device cpu_cluster 0 on > - chip cpu/intel/haswell > - device lapic 0 on end > - device lapic 0xacac off end > - end > - end > - > device domain 0 on > subsystemid 0x1849 0x0c00 inherit > > The resulting static.c is nearly identical, only two lines change: > > diff --git a/static.c b/static.c > index 4e0c4f4acb..6f149aff38 100644 > --- a/static.c > +++ b/static.c > @@ -149,9 +149,9 @@ STORAGE struct device _dev_0 = { > .link_list = &_dev_0_links[0], > .sibling = &_dev_1, > #if !DEVTREE_EARLY > - .chip_ops = &northbridge_intel_haswell_ops, > + .chip_ops = &cpu_intel_haswell_ops, > #endif > - .chip_info = &northbridge_intel_haswell_info_1, > + .chip_info = &cpu_intel_haswell_info_1, > .next=&_dev_1, > #if !DEVTREE_EARLY > #if CONFIG(GENERATE_SMBIOS_TABLES) chip_info picks up the struct below which chip it is in the devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Nov 2022 12:36:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to device...
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69301 ) Change subject: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree ...................................................................... soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/soc/intel/broadwell/northbridge.c 5 files changed, 20 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/69301/1 diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 3e2f289..440efdf 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,6 +15,7 @@ register "ec_present" = "true" device cpu_cluster 0 on + ops broadwell_cpu_bus_ops chip cpu/intel/haswell register "s0ix_enable" = "1" @@ -24,6 +25,7 @@ end device domain 0 on + ops broadwell_pci_domain_ops device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 2f2fa4a..fe09566 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -12,6 +12,7 @@ register "dq_pins_interleaved" = "true" device cpu_cluster 0 on + ops broadwell_cpu_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end @@ -19,6 +20,7 @@ end device domain 0 on + ops broadwell_pci_domain_ops device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 9090999..0becbbf 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -10,12 +10,14 @@ register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on + ops broadwell_cpu_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end end end device domain 0 on + ops broadwell_pci_domain_ops device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 60a06f4..ae98c9e 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -21,12 +21,14 @@ }" device cpu_cluster 0 on + ops broadwell_cpu_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end end end device domain 0 on + ops broadwell_pci_domain_ops device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index b65a758..bbde3d2 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -419,7 +419,7 @@ .devices = systemagent_ids }; -static struct device_operations pci_domain_ops = { +struct device_operations broadwell_pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, @@ -428,22 +428,12 @@ #endif }; -static struct device_operations cpu_bus_ops = { +struct device_operations broadwell_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void broadwell_enable(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - static void broadwell_init_pre_device(void *chip_info) { broadwell_run_reference_code(); @@ -451,6 +441,5 @@ struct chip_operations soc_intel_broadwell_ops = { CHIP_NAME("Intel Broadwell") - .enable_dev = &broadwell_enable, .init = &broadwell_init_pre_device, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/69301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Gerrit-Change-Number: 69301 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cpu/haswell/*.c: Move chip_ops to cpu cluster
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Arthur Heymans, Raul Rangel, Tristan Corrick, Tim Wawrzynczak, Angel Pons, Jonathon Hall, Alexander Couzens, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/haswell/*.c: Move chip_ops to cpu cluster ...................................................................... cpu/haswell/*.c: Move chip_ops to cpu cluster The cpu cluster is always present and it's the proper device to contain the settings that need to be applied to all cpus. Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/msi/h81m-p33/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb M src/northbridge/intel/haswell/northbridge.c M src/soc/intel/broadwell/northbridge.c 21 files changed, 79 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59314/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022