coreboot-gerrit November 2022

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[L] Change in coreboot[master]: mb/*: Remove lapic from devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Felix Singer, Frans Hendriks, Patrick Rudolph, Jonathan Zhang, Jeremy Soller, Angel Pons, Jonathon Hall, Michael Niewöhner, Piotr Król, Erik van den Bogaert, Tim Crawford, Tarun Tuli, Sean Rhodes, Nico Huber, Michał Żygowski, Maxim Polyakov, Johnny Lin, Christian Walter, Morgan Jang, Werner Zeh, Tim Chu. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69303 ) Change subject: mb/*: Remove lapic from devicetree ...................................................................... mb/*: Remove lapic from devicetree The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asus/p2b/devicetree.cb M src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb M src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb M src/mainboard/bostentech/gbyt4/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb M src/mainboard/facebook/fbg1701/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-d510ud/devicetree.cb M src/mainboard/google/cyan/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/rambi/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/smaug/devicetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/apollolake_rvp/devicetree.cb M src/mainboard/intel/cedarisland_crb/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb M src/mainboard/intel/d510mo/devicetree.cb M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/leafhill/devicetree.cb M src/mainboard/intel/minnow3/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/strago/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/ocp/deltalake/devicetree.cb M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/mainboard/portwell/m107/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_bsw/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/scaleway/tagada/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl-p/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/oryp8/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/mainboard/up/squared/devicetree.cb 112 files changed, 120 insertions(+), 351 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/69303/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index ab8787c..cc59992 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -100,9 +100,7 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 84eb3cf..38a56ca 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -32,9 +32,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1025 0x1037 inherit device ref system_agent on diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index a45127c..9bffafd 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -41,9 +41,7 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on # Host Bridge subsystemid 0x1849 0x191f diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 7ee69e4..a650552 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -1,9 +1,5 @@ chip northbridge/intel/i440bx # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC - end - end + device cpu_cluster 0 on end # APIC cluster device domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge diff --git a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb index ce36ce6..ed6224f 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb @@ -1,11 +1,5 @@ chip northbridge/intel/i440bx # Northbridge device cpu_cluster 0 on # (L)APIC cluster - chip cpu/intel/slot_1 # CPU socket 0 - device lapic 0 on end # Local APIC of CPU 0 - end - chip cpu/intel/slot_1 # CPU socket 1 - device lapic 1 on end # Local APIC of CPU 1 - end end device domain 0 on # PCI domain chip southbridge/intel/i82371eb # Southbridge diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb index b261a35..adcce28 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb @@ -1,11 +1,5 @@ chip northbridge/intel/i440bx # Northbridge device cpu_cluster 0 on # (L)APIC cluster - chip cpu/intel/slot_1 # CPU socket 0 - device lapic 0 on end # Local APIC of CPU 0 - end - chip cpu/intel/slot_1 # CPU socket 1 - device lapic 1 on end # Local APIC of CPU 1 - end end device domain 0 on # PCI domain chip southbridge/intel/i82371eb # Southbridge diff --git a/src/mainboard/bostentech/gbyt4/devicetree.cb b/src/mainboard/bostentech/gbyt4/devicetree.cb index 15a5d86..f115303 100644 --- a/src/mainboard/bostentech/gbyt4/devicetree.cb +++ b/src/mainboard/bostentech/gbyt4/devicetree.cb @@ -29,9 +29,7 @@ # Disable SLP_X stretching after SUS power well fail. register "disable_slp_x_stretch_sus_fail" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # SoC router device pci 02.0 on end # GFX diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index bfcc046..fe09382 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -55,9 +55,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x1401 inherit diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index d22f574..765d17c 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -35,9 +35,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x1313 inherit device ref system_agent on end diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb index 211ad4b..fc1d1ba 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -2,7 +2,6 @@ device cpu_cluster 0 on register "tcc_offset" = "12" register "eist_enable" = "true" - device lapic 0 on end end device domain 0 on subsystemid 0x1558 0x14a1 inherit diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb index a340fdc..a77a640 100644 --- a/src/mainboard/facebook/fbg1701/devicetree.cb +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -82,9 +82,7 @@ # CPLD requires continuous mode register "serirq_mode" = "SERIRQ_CONTINUOUS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # 8086 2280 - SoC router diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 05bcc12..a4a0906 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -212,9 +212,7 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 766d68f..916329e 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -5,11 +5,7 @@ register "use_crt" = "1" register "use_lvds" = "0" - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FCBGA559 # CPU - device lapic 0 on end # APIC - end - end + device cpu_cluster 0 on end # APIC cluster device domain 0 on # PCI domain subsystemid 0x105b 0x0d55 inherit device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index c30f272..d1ab7e9 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -2,11 +2,7 @@ chip northbridge/intel/i945 - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end register "pci_mmio_size" = "768" diff --git a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb index 9fb5ff5..a2f3c59 100644 --- a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb +++ b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb @@ -5,7 +5,6 @@ device cpu_cluster 0 on chip cpu/intel/socket_FCBGA559 - device lapic 0 on end end end device domain 0 on diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c968dfc..c987d3b 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -91,9 +91,7 @@ # Allow PCIe devices to wake system from suspend register "pcie_wake_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on # EDS Table 24-4, Figure 24-5 device pci 00.0 on end # 8086 2280 - SoC transaction router diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index a9de097..ea7f6a9 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -216,9 +216,7 @@ register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 1e9ffd9..3a78869 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -228,9 +228,7 @@ }" register "tcc_offset" = "10" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 5ecc77b..95d5368 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -305,9 +305,7 @@ }" register "tcc_offset" = "6" # TCC of 94C - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 9a3e619..f7c1819 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -81,9 +81,7 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 976d829..1af96c5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -195,9 +195,7 @@ register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index abf53b47..eec90bc 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index d26f6bd..c1f1a8c 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -227,9 +227,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index db4aeeb..8c1a7ab 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -249,9 +249,7 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 8583518..5ec1b66 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -264,9 +264,7 @@ .psys_pmax = 101, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index b8a1812..5d58a4b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -271,9 +271,7 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 03336f2..0755ed0 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -244,9 +244,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index c6c2d3d..8c5ea2c 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -230,9 +230,7 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 5c34792..e5c8565 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -250,9 +250,7 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 976d829..1af96c5 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -195,9 +195,7 @@ register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 1ebf1e8..532680b 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -53,9 +53,7 @@ # Disable SLP_X stretching after SUS power well fail. register "disable_slp_x_stretch_sus_fail" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # SoC router device pci 02.0 on end # GFX diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index a66cecf..79bd74c 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 1eecbb3..90ead5c 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 3dfb96b..7d4f097 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index 4e29eb5..5d4121b 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 51d28b8..ec474a8 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index c0aebd5..728ebe2 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -208,9 +208,7 @@ register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 903bcc6..f01950e 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -213,9 +213,7 @@ register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/smaug/devicetree.cb b/src/mainboard/google/smaug/devicetree.cb index 247085c..18cb1be 100644 --- a/src/mainboard/google/smaug/devicetree.cb +++ b/src/mainboard/google/smaug/devicetree.cb @@ -1,8 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only chip soc/nvidia/tegra210 - device cpu_cluster 0 on - end + device cpu_cluster 0 on end register "display_controller" = "TEGRA_ARM_DISPLAYA" register "xres" = "2560" diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 5dc62aa..4a575f8 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -7,9 +7,7 @@ register "eist_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x103c 0x2b5e inherit device pci 00.0 on end # Host bridge diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 9a5937e..de8b383 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -6,9 +6,7 @@ end chip soc/intel/alderlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index 5421dc3..ef361b0 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -7,9 +7,7 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb index e890082..ea8b4e6 100644 --- a/src/mainboard/intel/cedarisland_crb/devicetree.cb +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/xeon_sp/cpx - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host bridge device pci 04.0 on end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index e0ea3f2..051eba0 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index a145584..2269d74 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # FSP configuration register "RMT" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index af5fc2d..b6bf5a8 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # FSP configuration register "RMT" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index f20622c9..ce46c63 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 55b340c..b9fe423 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Enable eDP device register "DdiPortEdp" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index dc8874a..9c08023 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Enable eDP device register "DdiPortEdp" = "1" diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 4b5449f..efa60e8f 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -5,11 +5,7 @@ register "use_crt" = "1" register "use_lvds" = "0" - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FCBGA559 # CPU - device lapic 0 on end # APIC - end - end + device cpu_cluster 0 on end # APIC cluster device domain 0 on # PCI domain device pci 0.0 on end # Host Bridge device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index d3d1142..2c952bf 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 6ab391e..45fb736 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index c00502a..fa81935 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/icelake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 0d36f13..7b22268 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/icelake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index bae619811..bf1b235 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -109,9 +109,7 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 3fffc4a..5c5382f 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -150,9 +150,7 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_G5" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index deb9f38..bc068c6 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -157,9 +157,7 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_A7" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index 76362e6..add83fe 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -7,9 +7,7 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index 76362e6..add83fe 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -7,9 +7,7 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7cf13ec..fcd99ac 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -192,9 +192,7 @@ # Use default SD card detect GPIO configuration #register "sdcard_cd_gpio" = "GPP_A7" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 8d80095..932a5c7 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/alderlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 848b0c31..d44a1b6 100644 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -80,9 +80,7 @@ # Allow PCIe devices to wake system from suspend register "pcie_wake_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on # EDS Table 24-4, Figure 24-5 device pci 00.0 on end # 8086 2280 - SoC transaction router diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 002f07e..46bfd95 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -63,9 +63,7 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb index 9248c0c2..e77a172 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb @@ -2,9 +2,7 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Override USB port configuration register "usb_config_override" = "1" diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 20089df..7ce2480 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -5,9 +5,7 @@ register "enable_vtd" = "1" register "dptf_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 00.1 on end # DPTF diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 39c2e33..26feab4 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -152,9 +152,7 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index f6b3c8b..7d5839e 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -48,9 +48,7 @@ register "cstate_states" = "CSTATES_C1C6" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device gpio 0 alias pch_gpio on end diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 1f7c9eb..fbf0662 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -40,9 +40,7 @@ register "gen2_dec" = "0x000c0ca1" # IPMI KCS - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device gpio 0 alias pch_gpio on end diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 243a9ba..1abcd61 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1022 0x1410 inherit diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 8273a96..99353f4 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1022 0x1410 inherit diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index f399d8b..c4975cc 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1022 0x1410 inherit diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index c69401b..0aee11c 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1022 0x1410 inherit diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index d779672..3bc6737 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -79,9 +79,7 @@ # Allow PCIe devices to wake system from suspend register "pcie_wake_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # 8086 2280 - SoC router diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 70ff564..8c2dbda 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -136,9 +136,7 @@ register "DisableHeciRetry" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb index 4b750c0..02a1642 100644 --- a/src/mainboard/protectli/vault_bsw/devicetree.cb +++ b/src/mainboard/protectli/vault_bsw/devicetree.cb @@ -79,9 +79,7 @@ # Enable SERIRQ continuous register "serirq_mode" = "SERIRQ_CONTINUOUS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # 8086 2280 - SoC transaction router device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping GFX diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index feb8b9f..4e4cbac 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -189,9 +189,7 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb index a1fc9e1..ff21977 100644 --- a/src/mainboard/purism/librem_cnl/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/devicetree.cb @@ -41,9 +41,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 94b79f9..4f4b36f 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -149,9 +149,7 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b2cb360..1365d85 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -166,9 +166,7 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index b25b281..fd96940 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -15,7 +15,6 @@ ops sandybridge_cpu_bus_ops chip cpu/intel/model_206ax # Magic APIC ID to locate this chip - device lapic 0 on end register "acpi_c1" = "CPU_ACPI_C3" register "acpi_c2" = "CPU_ACPI_C6" diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb index e9932a3..4de8bb5 100644 --- a/src/mainboard/scaleway/tagada/devicetree.cb +++ b/src/mainboard/scaleway/tagada/devicetree.cb @@ -31,9 +31,7 @@ register "ipc2" = "0x00000000" # IPC2 register "ipc3" = "0x00000000" # IPC3 - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 81dae2e..8d6c589 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -7,9 +7,7 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index b4d9970..cee1967 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -7,9 +7,7 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index bb978f4..dad319e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index f1594d2b..b728438 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index e6e14cb..4fae59e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index c601106..c7f2f73 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index e2d2606..40739df 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 27b3b93..c48eb5a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb index c879fef..a8b163e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 319a8437..c3024ae 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 4109ec9..1743f1e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index abb6333..709d8e1 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 72e6de2..96011ea 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index a1def8d..9a71015 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -50,9 +50,7 @@ register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Actual device tree. - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index f67106f..edc8a16 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -49,9 +49,7 @@ LPC_IOE_EC_62_66" # Actual device tree. - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref igpu on end diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index c2728dc..cd8c480 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -64,9 +64,7 @@ register "PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED" # Actual device tree. - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref igpu on end diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 6f627bb..b4a08bf 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -26,9 +26,7 @@ register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 01.0 off end # CPU PCIe Port 10 (x16) diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 4f16bbd..94f1bdd 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -47,9 +47,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x65d1 inherit diff --git a/src/mainboard/system76/adl-p/devicetree.cb b/src/mainboard/system76/adl-p/devicetree.cb index 6a9f362..c2e450e 100644 --- a/src/mainboard/system76/adl-p/devicetree.cb +++ b/src/mainboard/system76/adl-p/devicetree.cb @@ -19,9 +19,7 @@ # Thermal register "tcc_offset" = "8" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref system_agent on end diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index b46dac0..59a1c14 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -50,9 +50,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x7714 inherit diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index da86024..96844ed 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -54,9 +54,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index c02a6ec..d25b18a 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -47,9 +47,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index e26fe62..3640be6 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -78,9 +78,7 @@ register "pmc_gpe0_dw2" = "PMC_GPP_D" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on #From CPU EDS(575683) diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 6322394..bcd1130 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -103,9 +103,7 @@ .dc_loadline = 310, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref system_agent on end diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 77ba265..2c5fc3d 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -54,9 +54,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x1401 inherit diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index bb75616..733d020 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -54,9 +54,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x95e6 inherit diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 7350dcd..a05b5bd 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -52,9 +52,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index 01593cb..000128d 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -79,9 +79,7 @@ register "pmc_gpe0_dw2" = "PMC_GPP_D" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x65f1 inherit diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index 0666a1a..cdd9c04 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -66,9 +66,7 @@ register "CnviBtCore" = "true" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref system_agent on end diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 63a9016..b153855 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -54,9 +54,7 @@ register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 128c1bb..867f3a5 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -20,9 +20,7 @@ # 0:HS400 (Default) 1:HS200 2:DDR50 register "emmc_host_max_speed" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x8086 0x7270 inherit device pci 00.0 on end # - Host Bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/69303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Gerrit-Change-Number: 69303 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans 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Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/intel/gm45: Remove apic 0 from devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Alexander Couzens. Hello Stefan Ott, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69300 to look at the new patch set (#6). Change subject: nb/intel/gm45: Remove apic 0 from devicetree ...................................................................... nb/intel/gm45: Remove apic 0 from devicetree This is added at runtime. Change-Id: Ife2865f91e3d046bc66e423b2054f56176f57fc6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb 3 files changed, 15 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/69300/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife2865f91e3d046bc66e423b2054f56176f57fc6 Gerrit-Change-Number: 69300 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: nb/intel/i945: Remove apic 0 from devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Alexander Couzens, Evgeny Zinoviev. Hello Alexander Couzens, Evgeny Zinoviev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69299 to look at the new patch set (#6). Change subject: nb/intel/i945: Remove apic 0 from devicetree ...................................................................... nb/intel/i945: Remove apic 0 from devicetree This is added at runtime. Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb 9 files changed, 21 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/69299/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a Gerrit-Change-Number: 69299 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: nb/intel/x4x: Remove apic 0 from devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Angel Pons, Alexander Couzens. Hello Stefan Ott, Angel Pons, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69298 to look at the new patch set (#6). Change subject: nb/intel/x4x: Remove apic 0 from devicetree ...................................................................... nb/intel/x4x: Remove apic 0 from devicetree This is added at runtime. Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p5ql-em/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb 18 files changed, 30 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69298/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73 Gerrit-Change-Number: 69298 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Angel Pons, Alexander Couzens. Hello Stefan Ott, Angel Pons, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69297 to look at the new patch set (#6). Change subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm ...................................................................... cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/cpu/intel/model_1067x/chip.h M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/intel/speedstep.h M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p5ql-em/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/northbridge/intel/gm45/chip.h M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/x4x/northbridge.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c 34 files changed, 97 insertions(+), 127 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/69297/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Gerrit-Change-Number: 69297 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Angel Pons, Alexander Couzens. Hello Stefan Ott, Angel Pons, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69295 to look at the new patch set (#7). Change subject: nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree ...................................................................... nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p5ql-em/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/foxconn/g41s-k/variants/g41m/overridetree.cb M src/mainboard/foxconn/g41s-k/variants/g41s-k/overridetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/northbridge/intel/x4x/northbridge.c 23 files changed, 92 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/69295/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/69295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Gerrit-Change-Number: 69295 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Alexander Couzens, Evgeny Zinoviev. Hello Alexander Couzens, Evgeny Zinoviev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69294 to look at the new patch set (#7). Change subject: nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree ...................................................................... nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/t60/variants/t60/overridetree.cb M src/mainboard/lenovo/t60/variants/z61t/overridetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/northbridge/intel/i945/northbridge.c 13 files changed, 34 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/69294/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/69294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Gerrit-Change-Number: 69294 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Stefan Ott, Alexander Couzens. Hello Stefan Ott, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69293 to look at the new patch set (#7). Change subject: nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree ...................................................................... nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/northbridge/intel/gm45/northbridge.c 4 files changed, 18 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/69293/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/69293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Gerrit-Change-Number: 69293 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: cpu/intel/model_206ax: Remove fake lapic device
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Arthur Heymans, Tristan Corrick, Angel Pons, Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#8) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59316 ) Change subject: cpu/intel/model_206ax: Remove fake lapic device ...................................................................... cpu/intel/model_206ax: Remove fake lapic device Instead of using a fake lapic device hook up the cpu cluster to chip cpu/intel/model_206ax. The lapic deive is also not needed as the mp init will allocate it for the BSP at runtime. Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb M src/northbridge/intel/sandybridge/northbridge.c 45 files changed, 223 insertions(+), 429 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/59316/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Gerrit-Change-Number: 59316 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: cpu/intel/sandybridge: Use enum for ACPI C states
by Arthur Heymans (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. Hello Angel Pons, Alexander Couzens, Evgeny Zinoviev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69292 to look at the new patch set (#6). Change subject: cpu/intel/sandybridge: Use enum for ACPI C states ...................................................................... cpu/intel/sandybridge: Use enum for ACPI C states Also remove the now unnecessary comments from the devicetree. Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/chip.h M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb 42 files changed, 149 insertions(+), 126 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/69292/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Gerrit-Change-Number: 69292 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022