coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/prodrive/hermes: Fix format mismatch
by Felix Held (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Patrick Rudolph, Christian Walter, Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69239 ) Change subject: mb/prodrive/hermes: Fix format mismatch ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6947c1a39b115a7c7f5da1c9becfd51f45fad9 Gerrit-Change-Number: 69239 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 07 Nov 2022 14:38:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/aldrlake: Update ME HFSTS register definition
by Rizwan Qureshi (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69286 ) Change subject: soc/intel/aldrlake: Update ME HFSTS register definition ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Can you please consider porting the CL for MTL? Sure, I will add to my todo list -- To view, visit https://review.coreboot.org/c/coreboot/+/69286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Gerrit-Change-Number: 69286 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 14:37:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-P
by Felix Held (Code Review) 07 Nov '22

07 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66097 ) Change subject: mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-P ...................................................................... mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-P This adds an initial mainboard code for mtlrvp, Intel Meteorlake reference platform. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66097 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Balaji Manigandan <balaji.manigandan(a)intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- A src/mainboard/intel/mtlrvp/Kconfig A src/mainboard/intel/mtlrvp/Kconfig.name A src/mainboard/intel/mtlrvp/devicetree.cb A src/mainboard/intel/mtlrvp/dsdt.asl 4 files changed, 80 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Balaji Manigandan: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve Sridhar Siricilla: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig new file mode 100644 index 0000000..3c29d3a --- /dev/null +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -0,0 +1,34 @@ +config BOARD_INTEL_MTLRVP_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + select SOC_INTEL_METEORLAKE + +config BOARD_INTEL_MTLRVP_P + select BOARD_INTEL_MTLRVP_COMMON + +if BOARD_INTEL_MTLRVP_COMMON + +config MAINBOARD_DIR + default "intel/mtlrvp" + +config MAINBOARD_PART_NUMBER + string + default "mtlrvp" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + +config MAINBOARD_FAMILY + string + default "Intel_mtlrvp" + +config VARIANT_DIR + string + default "mtlrvp_p" if BOARD_INTEL_MTLRVP_P + +config DEVICETREE + string + default "devicetree.cb" + +endif # BOARD_INTEL_MTLRVP_COMMON diff --git a/src/mainboard/intel/mtlrvp/Kconfig.name b/src/mainboard/intel/mtlrvp/Kconfig.name new file mode 100644 index 0000000..b643b94 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_MTLRVP_P + bool "Meteorlake-P RVP" diff --git a/src/mainboard/intel/mtlrvp/devicetree.cb b/src/mainboard/intel/mtlrvp/devicetree.cb new file mode 100644 index 0000000..ad261da --- /dev/null +++ b/src/mainboard/intel/mtlrvp/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/meteorlake + + device domain 0 on + device ref igpu on end + end +end diff --git a/src/mainboard/intel/mtlrvp/dsdt.asl b/src/mainboard/intel/mtlrvp/dsdt.asl new file mode 100644 index 0000000..82d11c6 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/dsdt.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/66097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8 Gerrit-Change-Number: 66097 Gerrit-PatchSet: 11 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1
by Felix Held (Code Review) 07 Nov '22

07 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69189 ) Change subject: soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1 ...................................................................... soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1 RTD3,_ON method sometimes can create delays during system boot. Even when the power is already up, kernel still tries to call _ON method to power up device, but it's unnecessary. RTD3._STA returns device power, so _ON method can check _STA and see if the power on process can be skipped BUG=b:249931687 TEST=system can boot to OS with RTD3 pcie storage and save ~80 ms on Crota. Suspend stress test passes 100 cycles Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69189 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 47 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index f99ae44..7a64734 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -143,10 +143,30 @@ static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config, - enum pcie_rp_type rp_type) + enum pcie_rp_type rp_type, + const struct device *dev) { + const struct device *parent = dev->bus->dev; + acpigen_write_method_serialized("_ON", 0); + /* The _STA returns current power status of device, so we can skip _ON + * if _STA returns 1 + * Example: + * Local0 = \_SB.PCI0.RP01.RTD3._STA () + * If ((Local0 == One)) + * { + * Return (One) + * } + */ + acpigen_write_store(); + acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA")); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP); + acpigen_write_return_op(ONE_OP); + acpigen_write_if_end(); + + /* When this feature is enabled, ONSK indicates if the previous _OFF was * skipped. If so, since the device was not in Off state, and the current * _ON can be skipped as well. @@ -448,7 +468,7 @@ } pcie_rtd3_acpi_method_status(config); - pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); + pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type, dev); pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); acpigen_pop_len(); /* PowerResource */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84 Gerrit-Change-Number: 69189 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/include/gpio_defs.h: Add comment for accuracy
by 9elements QA (Code Review) 07 Nov '22

07 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69209 ) Change subject: soc/amd/common/include/gpio_defs.h: Add comment for accuracy ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 1 / 14 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134116 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134115 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134114 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134113 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134112 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134111 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134110 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134109 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134108 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134106 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134105 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134104 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134102 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134101 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 Gerrit-Change-Number: 69209 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 14:35:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/adlrvp: Fix expected statement
by Felix Held (Code Review) 07 Nov '22

07 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66266 ) Change subject: mb/intel/adlrvp: Fix expected statement ...................................................................... mb/intel/adlrvp: Fix expected statement Switch cases expect a statement so move the default label. TEST: With BUILD_TIMELESS=1 binary remains identical. Change-Id: I9a5d39bb3cbde64f82fc90186b0f2fb64bcde595 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66266 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/memory_rpl.c 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/memory_rpl.c b/src/mainboard/intel/adlrvp/memory_rpl.c index a541fbf..8302a06 100644 --- a/src/mainboard/intel/adlrvp/memory_rpl.c +++ b/src/mainboard/intel/adlrvp/memory_rpl.c @@ -18,11 +18,11 @@ case ADL_P_DDR4_2: case ADL_P_DDR5_1: case ADL_P_DDR5_2: + default: return; case ADL_P_LP5_1: case ADL_P_LP5_2: mem_cfg->Lp5BankMode = 1; return; - default: } } -- To view, visit https://review.coreboot.org/c/coreboot/+/66266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a5d39bb3cbde64f82fc90186b0f2fb64bcde595 Gerrit-Change-Number: 66266 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT
by Werner Zeh (Code Review) 07 Nov '22

07 Nov '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69307 ) Change subject: mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT ...................................................................... mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT Provide timing parameter for SSDT generation to achieve the requested 100 kHz speed with a high accuracy. Test: Measure I2C bus clock, high and low times during I2C access from Linux and confirm they match the specification. Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/69307/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index d5d1277..3b54f24 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -111,9 +111,21 @@ register "common_soc_config" = "{ .i2c[1] = { .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 0x1e1, + .scl_lcnt = 0x1f4, + .sda_hold = 0x64 + }, }, .i2c[2] = { .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 0x1df, + .scl_lcnt = 0x1f4, + .sda_hold = 0x64 + }, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/69307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8 Gerrit-Change-Number: 69307 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OS
by Werner Zeh (Code Review) 07 Nov '22

07 Nov '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69306 ) Change subject: mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OS ...................................................................... mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OS In Linux, the I2C speed defaults to 400 kHz if there is no device registered in ACPI which requests a different speed. Due to board limitations (layout, bus load), 400 kHz are too fast which results in a timing violation. Therefore, add a dummy I2C device to both used I2C buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus speed in Linux accordingly. Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/69306/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 4109ec9..d5d1277 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -144,8 +144,21 @@ register "cap_charge" = "CHARGE_OFF" device i2c 0x52 on end # RTC RV3028-C7 end + # Add dummy I2C device to limit BUS speed to 100 kHz in OS + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end end - device pci 15.2 on end # I2C2 + device pci 15.2 on # I2C2 + # Add dummy I2C device to limit BUS speed to 100 kHz in OS + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end + end device pci 15.3 on end # I2C3 device pci 16.0 hidden end # Management Engine Interface 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa Gerrit-Change-Number: 69306 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Correct I2C base clock to 100 MHz
by Werner Zeh (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Lean Sheng Tan. Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69305 ) Change subject: soc/intel/elkhartlake: Correct I2C base clock to 100 MHz ...................................................................... soc/intel/elkhartlake: Correct I2C base clock to 100 MHz According to measurements Elkhart Lake seems to drive the internal I2C controllers with 100 MHz instead of the common 133 MHz. The datasheet itself is quite vague on this definition, just one place mentions that it is 100 MHz (register description for offset 0x94). This patch changes the I2C controller base frequency to 100 MHz. The verification was done by measuring the set up resulting I2C clock for both 100 and 400 kHz. Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69305/1 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 4343e85..8e3dc11 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -151,7 +151,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int - default 133 + default 100 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int -- To view, visit https://review.coreboot.org/c/coreboot/+/69305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2 Gerrit-Change-Number: 69305 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/i2c/designware: Add 100 MHz controller base clock
by Werner Zeh (Code Review) 07 Nov '22

07 Nov '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69304 ) Change subject: drivers/i2c/designware: Add 100 MHz controller base clock ...................................................................... drivers/i2c/designware: Add 100 MHz controller base clock There are SoCs (for instance Intel Elkhart Lake) that do use 100 MHz as the base clock for I2C controllers. To support them properly add a frequency setting for 100 MHz to the designware I2C controller driver. Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/69304/1 diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index ecd9e88..1e3163a 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -196,6 +196,13 @@ struct freq freq; } soc_clocks[] = { { + .clk_speed_mhz = 100, + .freq = { + .ticks = 100, + .ns = 1000, + }, + }, + { .clk_speed_mhz = 120, .freq = { .ticks = 120, -- To view, visit https://review.coreboot.org/c/coreboot/+/69304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769 Gerrit-Change-Number: 69304 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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