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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69307 )
Change subject: mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/69307/comment/dac956bb_7bddb8f9
PS1, Line 117: .scl_lcnt = 0x1f4,…
[View More]
> Maybe decimal? Since i2c designware driver use the decimal.
I have used hex format to stay consistent with the siemens/mc_apl mainboards. But I can switch to decimal if you insist.
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Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68871 )
Change subject: mem_chip_info: Update to new format
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Patchset:
PS4:
> Uff... I mean it would but I was really hoping I could finalize this now... […]
Let's finalize this now. I'm asking because multiple teams (healthd, factory, …
[View More]odm, ...) are trying to identify the DRAM correctly. And with the deprecation of mosys, they need a source for DRAM info, so if we end up implmenting only partial info here, then the new requests may come soon.
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Arthur Heymans has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/69361 )
Change subject: cpu/*: Drop PARALLEL_MP leftovers
......................................................................
cpu/*: Drop PARALLEL_MP leftovers
These symbols and codepaths are unused now so drop them.
Change-Id: I7c46c36390f116f8f8920c06e539075e60c7118c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
D src/cpu/…
[View More]intel/hyperthreading/Makefile.inc
D src/cpu/intel/hyperthreading/intel_sibling.c
M src/cpu/intel/model_f3x/model_f3x_init.c
M src/cpu/x86/Kconfig.debug_cpu
D src/include/cpu/intel/hyperthreading.h
M src/mainboard/emulation/qemu-i440fx/northbridge.c
6 files changed, 13 insertions(+), 126 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/69361/3
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69312 )
Change subject: mb/google/nissa/var/xivu: Add Hynix new memory support
......................................................................
Patch Set 1: Code-Review+2
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69305 )
Change subject: soc/intel/elkhartlake: Correct I2C base clock to 100 MHz
......................................................................
Patch Set 1: Code-Review+2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68893 )
Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
......................................................................
Patch Set 11:
(2 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162892):
https://review.coreboot.org/c/coreboot/+/68893/comment/…
[View More]6652ec54_1f11ac8b
PS11, Line 8:
Possible repeated word: 'are'
File src/cpu/x86/mp_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162892):
https://review.coreboot.org/c/coreboot/+/68893/comment/56fa2a67_79cf147f
PS11, Line 493: if (!cpu->enabled) {
braces {} are not necessary for any arm of this statement
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69339 )
Change subject: Revert "mb/aopen/dxplplusu: Remove board"
......................................................................
Patch Set 3:
(1 comment)
File src/cpu/intel/model_f2x/model_f2x_init.c:
https://review.coreboot.org/c/coreboot/+/69339/comment/05ba2083_3149977b
PS2, Line 17: if (!…
[View More]intel_ht_sibling()) {
: /* MTRRs are shared between threads */
: x86_setup_mtrrs();
: x86_mtrr_check();
:
: /* Update the microcode */
: intel_update_microcode_from_cbfs();
: }
:
: /* Start up my CPU siblings */
: intel_sibling_init(cpu);
> This can be dropped if mp_ops has […]
Done but not tested
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69307 )
Change subject: mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/69307/comment/2b5169db_d1016dbf
PS1, Line 117: .scl_lcnt = 0x1f4,…
[View More]
Maybe decimal? Since i2c designware driver use the decimal.
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