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Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables
......................................................................
Patch Set 25: Verified-1
(4 comments)
File src/soc/sifive/fu540/ux00ddr.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162933):
https://review.coreboot.org/c/coreboot/+/63074/comment/ddbf1b9c_f0e03b80
PS25, Line 179: /* char slicelsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162933):
https://review.coreboot.org/c/coreboot/+/63074/comment/89269c04_d948e7cd
PS25, Line 180: /* char slicemsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162933):
https://review.coreboot.org/c/coreboot/+/63074/comment/3c83a392_0b87d5e1
PS25, Line 181: /* slicelsc += (dq % 10); */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162933):
https://review.coreboot.org/c/coreboot/+/63074/comment/162ad12a_42140036
PS25, Line 182: /* slicemsc += (dq / 10); */
code indent should use tabs where possible
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Change subject: arch/x86/memmove: Add 64bit version
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162929):
https://review.coreboot.org/c/coreboot/+/69231/comment/25363554_3d4d3527
PS7, Line 10:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69231
to look at the new patch set (#7).
Change subject: arch/x86/memmove: Add 64bit version
......................................................................
arch/x86/memmove: Add 64bit version
The 64bit handles 64bit input variables properly.
TESTED: Both qemu and real hardware can use LZ4 properly which use this code
Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Makefile.inc
R src/arch/x86/memmove_32.c
A src/arch/x86/memmove_64.S
3 files changed, 225 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/69231/7
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Change subject: mb/google/brya/marasov: Enable ISH driver and firmware name
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> marasov don't support ISH, we open ISH for enable pcie D18:F7 UFS
Based on the FW config (STORAGE STORAGE_UFS), if UFS is not enabled then due to probe I believe the ISH device and the relevant chip driver will be skipped.
```
device ref ish on
chip drivers/intel/ish
register "firmware_name" = ""adl_ish_lite.bin""
device generic 0 on end
end
probe STORAGE STORAGE_UFS
end
```
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Hello build bot (Jenkins), Tarun Tuli, Martin L Roth, Reka Norman,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/65606
to look at the new patch set (#10).
Change subject: profiler: Add basic profiler with cbmem support
......................................................................
profiler: Add basic profiler with cbmem support
How to generate flamegraph:
1. Build and run coreboot with CONFIG_PROFILER
2. `cbmem -p > profiler.dump`
3. `util/profiler_tools/profiler_addr2line.py -e ramstage.debug \
-o collapsed.txt profiler.dump`
4. `flamegraph.pl collapsed.txt > graph.svg`
Overhead is about 8-15% depending on platform.
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I5665922b1109ee9305274294c93de577f1bf9ae2
---
M Makefile.inc
M src/Kconfig
M src/arch/arm64/arch_timer.c
M src/arch/arm64/armv8/exception.c
M src/arch/arm64/transition.c
M src/arch/x86/c_start.S
M src/arch/x86/cpu.c
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/commonlib/bsd/include/commonlib/bsd/compiler.h
A src/commonlib/bsd/include/commonlib/bsd/profiler.h
M src/lib/Makefile.inc
A src/lib/profiler.c
M util/cbmem/cbmem.c
A util/profiler_tools/profiler_addr2line.py
14 files changed, 551 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/65606/10
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Change subject: mb/google/brya/marasov: Add memory config for marasov
......................................................................
Patch Set 9: Code-Review+1
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Change subject: mb/google/brya/marasov: Enable ISH driver and firmware name
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
marasov don't support ISH, we open ISH for enable pcie D18:F7 UFS
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Change subject: ec/google/chromeec: Deprecate dev_index from google_chromeec_reboot
......................................................................
Patch Set 1: Code-Review+2
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