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Change subject: mem_chip_info: Update to new format
......................................................................
Patch Set 5:
(1 comment)
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/68871/comment/9864a45d_bc1e227a
PS3, Line 129: ddr->mrr_info.mr8_density[r]
> Ack
Wait, I think `ddr->mrr_info.mr8_density[r]` is in bytes instead of megabits. Xixi, please confirm.
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Change subject: mb/*: Remove lapic from devicetree
......................................................................
Patch Set 5: Code-Review+1
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Change subject: mb/starlabs/starbook: Add Alder Lake StarBook Mk VI variant
......................................................................
Patch Set 26:
This change is ready for review.
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Change subject: soc/intel/common: add units to soc_power_limits_config elements
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/starlabs/lite/devtree.c:
https://review.coreboot.org/c/coreboot/+/69206/comment/f2dad7c0_14adbb1a
PS1, Line 43: cfg->tcc_offset = 5;
> I will keep original style.
That's the spirit
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Change subject: soc/intel/common: add units to soc_power_limits_config elements
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/starlabs/lite/devtree.c:
https://review.coreboot.org/c/coreboot/+/69206/comment/39c56181_124502cc
PS1, Line 43: cfg->tcc_offset = 5;
> Editing other peoples patches isn't the done thing.
I will keep original style.
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69377 )
Change subject: mb/google/brya/marasov: Enable ISH driver and firmware name
......................................................................
mb/google/brya/marasov: Enable ISH driver and firmware name
BUG=b:234776154
TEST=Build and boot Marasov UFS, copy ISH firmware to host
file system /lib/firmware/intel/adl_ish_lite.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adl_ish_lite.bin loaded
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ic53a3cbdf83825adc27f37877a14f4f405d4a5ee
---
M src/mainboard/google/brya/variants/marasov/overridetree.cb
1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/69377/1
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index 3f9dcfa..6b6fd3e 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -126,6 +126,10 @@
probe STORAGE STORAGE_NVME
end
device ref ish on
+ chip drivers/intel/ish
+ register "firmware_name" = ""adl_ish_lite.bin""
+ device generic 0 on end
+ end
probe STORAGE STORAGE_UFS
end
device ref ufs on
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Subrata Banik has uploaded a new patch set (#4) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/69364 )
Change subject: mb/google/brya/marasov: Update devicetree setting for marasov
......................................................................
mb/google/brya/marasov: Update devicetree setting for marasov
update devicetree setting per the schematic
BUG=b:254365935
BRANCH=None
TEST=Built successfully
Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com>
Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a
---
M src/mainboard/google/brya/variants/marasov/overridetree.cb
1 file changed, 258 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/69364/4
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Subrata Banik has uploaded a new patch set (#2) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/69311 )
Change subject: mb/google/var/marasov: Generate SPD ID for supported memory parts
......................................................................
mb/google/var/marasov: Generate SPD ID for supported memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
MT62F1G32D4DR-031 WT:B 4 (0100)
K3LKBKB0BM-MGCP 5 (0101)
BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id
Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com>
Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7
---
M src/mainboard/google/brya/variants/marasov/memory/Makefile.inc
M src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt
3 files changed, 43 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/69311/2
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69206 )
Change subject: soc/intel/common: add units to soc_power_limits_config elements
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/starlabs/lite/devtree.c:
https://review.coreboot.org/c/coreboot/+/69206/comment/5d0541ac_3ff48a2f
PS1, Line 43: cfg->tcc_offset = 5;
> Hi Sean, […]
Editing other peoples patches isn't the done thing.
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68871 )
Change subject: mem_chip_info: Update to new format
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
src/soc/mediatek/common/emi.c:22:40: error: 'const struct mem_chip_info' has no member named 'num_channels'
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