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Change subject: amdfwtool: Add support for 32M image size
......................................................................
Patch Set 3:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/69043/comment/6b0f23c2_ad1c2e99
PS1, Line 2302: case 0xFFFA0000: /* Fall through */
: case 0xFFF20000: /* Fall through */
: case 0xFFE20000: /* Fall through */
: case 0xFFC20000: /* Fall through */
: case 0xFF820000: /* Fall through */
: case 0xFF020000: /* Fall through */
> Note that this is just not correct. […]
That is a legacy misleading, which connects to much code and settings.
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Change subject: mb/google/nissa/var/craask: Modify DPTF related settings
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
File src/mainboard/google/brya/variants/craask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/68523/comment/74fb0e3f_de093cd4
PS3, Line 154: .time_window_min = 28 * MSECS_PER_SEC,
> Done. Set pl2.time_window_min/max to 1. […]
Done
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Change subject: mb/google/nissa/var/craask: Modify DPTF related settings
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/craask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/68523/comment/0047d9d9_8e8fe2ba
PS3, Line 154: .time_window_min = 28 * MSECS_PER_SEC,
> MSECS_PER_SEC value is 1000, so the above interprets to 1000 msec. Actula value is 976 us = ~1ms. […]
Done. Set pl2.time_window_min/max to 1.
PLease help to review, thanks!
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Change subject: soc/amd/morgana: Add 32M support
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/amd/birman/board.fmd:
https://review.coreboot.org/c/coreboot/+/69150/comment/04aa1f7b_8f3020db
PS1, Line 1: FLASH@0xFE000000 32M {
: BIOS {
: EC 4K
: AMDFW @128K 13M
: FMAP @16M 4K
> These changes should also be made on chromeos. […]
Done
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Change subject: soc/amd/morgana: Add 32M support
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69150/comment/eab72aeb_bb8393ac
PS1, Line 24: If coreboot need to access bottom 16M, which in fact doesn't seem to
> > 'implimented' may be misspelled - perhaps 'implemented'? […]
Done
https://review.coreboot.org/c/coreboot/+/69150/comment/badc5cbb_654bcd9b
PS1, Line 27: The bit 15 of soft fuse decides which (top or bottom) 16M is mapped to
> should this be bit 14?
Done
File src/soc/amd/morgana/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69150/comment/dc4c6eae_d04f2885
PS1, Line 118: PSP_SOFTFUSE_BITS += 15
> should this be bit 14?
Done
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Change subject: amdfwtool: Add definition of instance for PSP entry
......................................................................
Patch Set 3:
(1 comment)
File util/amdfwtool/amdfwtool.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163068):
https://review.coreboot.org/c/coreboot/+/69044/comment/4877bdf3_992f436d
PS3, Line 166: } __attribute__((packed));
Prefer __packed over __attribute__((packed))
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Change subject: amdfwtool: Add support for 32M image size
......................................................................
Patch Set 3:
(1 comment)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163066):
https://review.coreboot.org/c/coreboot/+/69043/comment/b142140e_1a1b3b64
PS3, Line 2308: case 0xFE020000: /* Fall through */
Prefer 'fallthrough;' over fallthrough comment
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Hello Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69150
to look at the new patch set (#2).
Change subject: soc/amd/morgana: Add 32M support
......................................................................
soc/amd/morgana: Add 32M support
The 32M has to be divided into 2 16M parts, top and bottom. We can
only map one part at one time. By default, the bottom 16M is mapped to
0xFF000000-0xFFFFFFFF. By this default setting, the address in the
image is not the actual phyical address. So we need to convert the
address, or map the upper 16M instead (the easier way UEFI BIOS
does). So we push all the modules with running code, like romstage,
ramstage, even the fmap table, to upper 16M. For the bootblock part,
which is loaded by bootloader, it is unchanged as a tiny relocatable
image in bottom 16M in amdfw.rom.
Since the amdfw.rom is not in CFBS, we put it in fmap.
We put only EC FWs and PSP FWs in the botttom, where the PSP can
load.
If coreboot need to access bottom 16M, which in fact doesn't seem to
be necessary, can be implemented by SMN command.
The bit 14 of soft fuse decides which (top or bottom) 16M is mapped to
4G-16M.
BUG=b:255374782
Change-Id: Ia0b5a75f828033b29c378bed9a939b23d7f19140
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/mainboard/amd/birman/Kconfig
M src/mainboard/amd/birman/board.fmd
M src/mainboard/amd/birman/chromeos.fmd
M src/soc/amd/morgana/Kconfig
M src/soc/amd/morgana/Makefile.inc
5 files changed, 53 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/69150/2
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Hello build bot (Jenkins), Zheng Bao, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69043
to look at the new patch set (#3).
Change subject: amdfwtool: Add support for 32M image size
......................................................................
amdfwtool: Add support for 32M image size
The bottom 16M is not accessible by x86 by default. The addresses in
the tables are all relative value to base address. So, the address
0xFE020000 is not the actual phyical address. It is only for adding
the amdfw.rom into the image.
Change-Id: Ica050dfecd258fdd6717c308907d7d4d2e85b926
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69043/3
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