coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/nissa/var/xivu: Add Hynix new memory support
by Eric Lai (Code Review) 09 Nov '22

09 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69312 ) Change subject: mb/google/nissa/var/xivu: Add Hynix new memory support ...................................................................... mb/google/nissa/var/xivu: Add Hynix new memory support Add new ram_id:0 (0000) for memory part H9JCNNNCP3MLYR-N6E. DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 0 (0000) BUG=b:257867226 TEST=Use part_id_gen to generate related settings and emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: If663afbcd2e0457636f4a1c7475f1e3e40f0dd96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69312 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/variants/xivu/memory/Makefile.inc M src/mainboard/google/brya/variants/xivu/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/xivu/memory/mem_parts_used.txt 3 files changed, 27 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Eric Lai: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/xivu/memory/Makefile.inc b/src/mainboard/google/brya/variants/xivu/memory/Makefile.inc index 8535997..8487277 100644 --- a/src/mainboard/google/brya/variants/xivu/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/xivu/memory/Makefile.inc @@ -4,7 +4,7 @@ # ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/xivu/memory/ src/mainboard/google/brya/variants/xivu/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = K3LKBKB0BM-MGCP SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 3(0b0011) Parts = K3LKCKC0BM-MGCP diff --git a/src/mainboard/google/brya/variants/xivu/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/xivu/memory/dram_id.generated.txt index 579a4fa..a462e5f 100644 --- a/src/mainboard/google/brya/variants/xivu/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/xivu/memory/dram_id.generated.txt @@ -7,5 +7,6 @@ MT62F1G32D4DR-031 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 1 (0001) +H9JCNNNCP3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 2 (0010) K3LKCKC0BM-MGCP 3 (0011) diff --git a/src/mainboard/google/brya/variants/xivu/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/xivu/memory/mem_parts_used.txt index 2d8f7be..6d01c57 100644 --- a/src/mainboard/google/brya/variants/xivu/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/xivu/memory/mem_parts_used.txt @@ -12,5 +12,6 @@ MT62F1G32D4DR-031 WT:B MT62F512M32D2DR-031 WT:B H9JCNNNBK3MLYR-N6E +H9JCNNNCP3MLYR-N6E K3LKBKB0BM-MGCP K3LKCKC0BM-MGCP -- To view, visit https://review.coreboot.org/c/coreboot/+/69312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If663afbcd2e0457636f4a1c7475f1e3e40f0dd96 Gerrit-Change-Number: 69312 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by build bot (Jenkins) (Code Review) 09 Nov '22

09 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... Patch Set 2: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163077): https://review.coreboot.org/c/coreboot/+/69386/comment/20b1daf3_29e4dd60 PS2, Line 14: https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-trans… Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Nov 2022 07:52:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/ehl: Add EHL MDIO operation
by Werner Zeh (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Mario Scheithauer, Angel Pons, Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add EHL MDIO operation ...................................................................... Patch Set 1: (12 comments) File src/soc/intel/elkhartlake/include/soc/mdio.h: https://review.coreboot.org/c/coreboot/+/69383/comment/b49f8f2e_37167dcf PS1, Line 8: Address address https://review.coreboot.org/c/coreboot/+/69383/comment/e6b893bd_cee68c9f PS1, Line 10: Address address https://review.coreboot.org/c/coreboot/+/69383/comment/d76e7694_f5258f55 PS1, Line 11: Address address https://review.coreboot.org/c/coreboot/+/69383/comment/96d1bf09_df91e8c5 PS1, Line 12: Trailing Clocks trailing clocks https://review.coreboot.org/c/coreboot/+/69383/comment/04ba4d25_9fc59df9 PS1, Line 18: Data data https://review.coreboot.org/c/coreboot/+/69383/comment/d73a7ce2_29329cbd PS1, Line 21: mdio Since you spell MDIO uppercase in comments elsewhere, I would stay consistent in all comments. File src/soc/intel/elkhartlake/mdio.c: https://review.coreboot.org/c/coreboot/+/69383/comment/c4403d72_7bd3daff PS1, Line 33: /* Get the base address of the I/O registers in memory space */ Do we need this comment here? It decreases code readability while it does not provide any additional information that cannot be derived from the code itself. https://review.coreboot.org/c/coreboot/+/69383/comment/8310afb8_84633218 PS1, Line 46: status = phy_gmii_ready(io_mem_base); : if (status == CB_ERR) { You can get rid of the extra status variable here: if (phy_gmii_ready(io_mem_base) == CB_ERROR) { If you do not use it elsewhere, why should we have it at all? https://review.coreboot.org/c/coreboot/+/69383/comment/da3d1a57_d56b6ce9 PS1, Line 52: BIOS_DEBUG Should we move this to SPEW-level? https://review.coreboot.org/c/coreboot/+/69383/comment/1fc89c8f_3fee9d65 PS1, Line 61: /* Get the base address of the I/O registers in memory space */ Same here. https://review.coreboot.org/c/coreboot/+/69383/comment/534b26cc_9a20eafe PS1, Line 75: status = phy_gmii_ready(io_mem_base); : if (status == CB_ERR) Same status-comment applies here. File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/69383/comment/256e6c31_83623612 PS1, Line 41: specified mdio device is missing mdio ops! Since you have access to the device, print the device path here instead of the "specified mdio device"? -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 07:52:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/i2c/sx9324: Add support for Linux's SX9324 driver
by Eric Lai (Code Review) 09 Nov '22

09 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69192 ) Change subject: drivers/i2c/sx9324: Add support for Linux's SX9324 driver ...................................................................... drivers/i2c/sx9324: Add support for Linux's SX9324 driver SX9324 driver is updated per Linux's documentation found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Doc… Supporting logic for the deprecated SX932x driver is hence guarded by DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER This patch by itself does not introduce functional changes to any board. The legacy SX932x Linux driver never reached upstream Linux and is only available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted a different implementation named SX9324 and has been available since 5.4. Ideally all variants should adopt the new driver; however, during the transition phase, coreboot must support both drivers. It is better to have a single firmware build that can work with both Linux kernel drivers by specifying both sets of properties. Legacy driver support should be deleted once all variants finish migration. BUG=b:242662878 TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy SX932x driver are identical w/ and w/o this patch (Tested on Craask and Nivviks) Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b Signed-off-by: Victor Ding <victording(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/drivers/i2c/sx9324/Kconfig M src/drivers/i2c/sx9324/chip.h M src/drivers/i2c/sx9324/registers.h M src/drivers/i2c/sx9324/sx9324.c M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/zork/Kconfig.name 7 files changed, 224 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/drivers/i2c/sx9324/Kconfig b/src/drivers/i2c/sx9324/Kconfig index 77f6967..222ff8d 100644 --- a/src/drivers/i2c/sx9324/Kconfig +++ b/src/drivers/i2c/sx9324/Kconfig @@ -4,3 +4,19 @@ depends on HAVE_ACPI_TABLES help Board has a Semtech SX9324 proximity sensor. + +config DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + bool + default n + depends on DRIVERS_I2C_SX9324 + help + Board may use the legacy sx932x linux driver. + This option is mainly to ease migrating from the legacy driver to the + Linux one and should be deleted once all variants finish migration. + This driver never reached upstream Linux and is only available in + ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted a different + implementation named SX9324 and has been available since 5.4. + Ideally all variants should adopt the new driver; however, during the + transition phase, coreboot must support both drivers. By selecting this + option, coreboot's SX9324 driver will specify all properties to work with + both Linux kernel drivers. diff --git a/src/drivers/i2c/sx9324/chip.h b/src/drivers/i2c/sx9324/chip.h index 9c9dd3c..47910fb 100644 --- a/src/drivers/i2c/sx9324/chip.h +++ b/src/drivers/i2c/sx9324/chip.h @@ -23,7 +23,148 @@ /* IO-APIC interrupt */ struct acpi_irq irq; + + /* + semtech,ph0-pin: + description: | + Array of 3 entries. Index represent the id of the CS pin. + Value indicates how each CS pin is used during phase 0. + Each of the 3 pins have the following value - + 0 : unused (high impedance) + 1 : measured input + 2 : dynamic shield + 3 : grounded. + For instance, CS0 measured, CS1 shield and CS2 ground is [1, 2, 3] + items: + enum: [ 0, 1, 2, 3 ] + minItems: 3 + maxItems: 3 + */ + uint64_t ph0_pin[3]; + + /* + semtech,ph1-pin: + Same as ph0-pin for phase 1. + */ + uint64_t ph1_pin[3]; + + /* + semtech,ph2-pin: + Same as ph0-pin for phase 2. + */ + uint64_t ph2_pin[3]; + + /* + semtech,ph3-pin: + Same as ph0-pin for phase 3. + */ + uint64_t ph3_pin[3]; + + /* + semtech,ph01-resolution: + enum: [8, 16, 32, 64, 128, 256, 512, 1024] + description: + Capacitance measurement resolution. For phase 0 and 1. + Higher the number, higher the resolution. + default: 128 + */ + uint64_t ph01_resolution; + + /* + semtech,ph23-resolution: + Same as ph01-resolution for phase 2 and 3. + */ + uint64_t ph23_resolution; + + /* + semtech,startup-sensor: + enum: [0, 1, 2, 3] + default: 0 + description: | + Phase used for start-up proximity detection. + It is used when we enable a phase to remove static offset and measure + only capacitance changes introduced by the user. + */ + uint64_t startup_sensor; + + /* + semtech,ph01-proxraw-strength: + minimum: 0 + maximum: 7 + default: 1 + description: + PROXRAW filter strength for phase 0 and 1. A value of 0 represents off, + and other values represent 1-1/2^N. + */ + uint64_t ph01_proxraw_strength; + + /* + semtech,ph23-proxraw-strength: + Same as proxraw-strength01, for phase 2 and 3. + */ + uint64_t ph23_proxraw_strength; + + /* + semtech,avg-pos-strength: + enum: [0, 16, 64, 128, 256, 512, 1024, 4294967295] + default: 16 + description: | + Average positive filter strength. A value of 0 represents off and + UINT_MAX (4294967295) represents infinite. Other values + represent 1-1/N. + */ + uint64_t avg_pos_strength; + + /* + semtech,cs-idle-sleep: + description: + State of CS pins during sleep mode and idle time. + enum: + - hi-z + - gnd + - vdd + */ + const char *cs_idle_sleep; + + /* + semtech,int-comp-resistor: + description: + Internal resistor setting for compensation. + enum: + - lowest + - low + - high + - highest + */ + const char *int_comp_resistor; + + /* + semtech,input-precharge-resistor-ohms: + default: 4000 + multipleOf: 2000 + minimum: 0 + maximum: 30000 + description: + Pre-charge input resistance in Ohm. + */ + uint64_t input_precharge_resistor_ohms; + + /* + semtech,input-analog-gain: + minimum: 0 + maximum: 3 + description: | + Defines the input antenna analog gain + 0: x1.247 + 1: x1 (default) + 2: x0.768 + 3: x0.552 + */ + uint64_t input_analog_gain; + +#if CONFIG(DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER) #include "registers.h" +#endif }; #undef REGISTER diff --git a/src/drivers/i2c/sx9324/registers.h b/src/drivers/i2c/sx9324/registers.h index 2e22572..2035463 100644 --- a/src/drivers/i2c/sx9324/registers.h +++ b/src/drivers/i2c/sx9324/registers.h @@ -4,6 +4,10 @@ #error "define REGISTER(NAME) before including this file" #endif +#if !CONFIG(DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER) +#error "This file is only to support the legacy sx932x linux driver" +#endif + REGISTER(reg_adv_ctrl0); REGISTER(reg_adv_ctrl1); REGISTER(reg_adv_ctrl2); diff --git a/src/drivers/i2c/sx9324/sx9324.c b/src/drivers/i2c/sx9324/sx9324.c index 2ca9f36..3678491 100644 --- a/src/drivers/i2c/sx9324/sx9324.c +++ b/src/drivers/i2c/sx9324/sx9324.c @@ -56,7 +56,23 @@ /* DSD */ dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer_array(dsd, "semtech,ph0-pin", config->ph0_pin, ARRAY_SIZE(config->ph0_pin)); + acpi_dp_add_integer_array(dsd, "semtech,ph1-pin", config->ph1_pin, ARRAY_SIZE(config->ph1_pin)); + acpi_dp_add_integer_array(dsd, "semtech,ph2-pin", config->ph2_pin, ARRAY_SIZE(config->ph2_pin)); + acpi_dp_add_integer_array(dsd, "semtech,ph3-pin", config->ph3_pin, ARRAY_SIZE(config->ph3_pin)); + acpi_dp_add_integer(dsd, "semtech,ph01-resolution", config->ph01_resolution); + acpi_dp_add_integer(dsd, "semtech,ph23-resolution", config->ph23_resolution); + acpi_dp_add_integer(dsd, "semtech,startup-sensor", config->startup_sensor); + acpi_dp_add_integer(dsd, "semtech,ph01-proxraw-strength", config->ph01_proxraw_strength); + acpi_dp_add_integer(dsd, "semtech,ph23-proxraw-strength", config->ph23_proxraw_strength); + acpi_dp_add_integer(dsd, "semtech,avg-pos-strength", config->avg_pos_strength); + acpi_dp_add_integer(dsd, "semtech,input-precharge-resistor-ohms", config->input_precharge_resistor_ohms); + acpi_dp_add_integer(dsd, "semtech,input-analog-gain", config->input_analog_gain); + acpi_dp_add_string(dsd, "semtech,cs-idle-sleep", config->cs_idle_sleep); + acpi_dp_add_string(dsd, "semtech,int-comp-resistor", config->int_comp_resistor); +#if CONFIG(DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER) #include "registers.h" +#endif acpi_dp_write(dsd); acpigen_pop_len(); /* Device */ diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 4ead1f9..3c755c6 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -40,6 +40,7 @@ select SOC_INTEL_RAPTORLAKE select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CRASHLOG @@ -85,6 +86,7 @@ select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE @@ -139,6 +141,7 @@ select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_SKOLAS4ES @@ -147,6 +150,7 @@ select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_TAEKO @@ -257,6 +261,7 @@ select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_XIVU diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 45cc117..4f2fa04 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -5,6 +5,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_DEDEDE @@ -108,6 +109,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR @@ -124,6 +126,7 @@ select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_BLIPPER @@ -177,6 +180,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_BEADRIX @@ -185,6 +189,7 @@ select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER config BOARD_GOOGLE_SHOTZO bool "-> Shotzo" diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 7ba518a..4e6cfc5 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -8,6 +8,7 @@ bool "-> Vilboz (Lenovo 100e/300e Gen3 AMD)" select BOARD_GOOGLE_BASEBOARD_DALBOZ select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER config BOARD_GOOGLE_EZKINIL bool "-> Ezkinil (Acer Chromebook Spin 514)" -- To view, visit https://review.coreboot.org/c/coreboot/+/69192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b Gerrit-Change-Number: 69192 Gerrit-PatchSet: 9 Gerrit-Owner: Victor Ding <victording(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: drivers/i2c/sx9324: Add support for Linux's SX9324 driver
by Eric Lai (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Victor Ding, Jason Nien, Martin Roth. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69192 ) Change subject: drivers/i2c/sx9324: Add support for Linux's SX9324 driver ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b Gerrit-Change-Number: 69192 Gerrit-PatchSet: 8 Gerrit-Owner: Victor Ding <victording(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Ding <victording(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 07:51:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/device: Add MDIO operation
by Mario Scheithauer (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Mario Scheithauer. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69382 to look at the new patch set (#2). Change subject: src/device: Add MDIO operation ...................................................................... src/device: Add MDIO operation The interface is necessary for SOC specific MDIO access. Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/device/Makefile.inc A src/device/mdio.c M src/include/device/device.h A src/include/device/mdio.h 4 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/69382/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2 Gerrit-Change-Number: 69382 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/craask: Disable stylus GPIO pins based on fw_config
by Eric Lai (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Tyler Wang, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69138 ) Change subject: mb/google/nissa/craask: Disable stylus GPIO pins based on fw_config ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e3a2583187c8a8e2616a5272b5a7a61debe982b Gerrit-Change-Number: 69138 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 07:44:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/device: Add MDIO operation
by Werner Zeh (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69382 ) Change subject: src/device: Add MDIO operation ...................................................................... Patch Set 1: (3 comments) File src/device/mdio.c: https://review.coreboot.org/c/coreboot/+/69382/comment/7c8e214e_cf99236b PS1, Line 11: operations. Please add a '\n' here for a proper line break. https://review.coreboot.org/c/coreboot/+/69382/comment/35371aea_984f6ff5 PS1, Line 11: mdio Shall we spell it upper case in log messages? File src/include/device/mdio.h: https://review.coreboot.org/c/coreboot/+/69382/comment/175683fd_11f58fcb PS1, Line 6: struct device; You should include <device/device.h> here and avoid the forward declaration of 'struct device' In addition, include <stdint.h> to provide types for uint*_t. -- To view, visit https://review.coreboot.org/c/coreboot/+/69382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2 Gerrit-Change-Number: 69382 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 06:53:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/generic/ioapic: Use register_new_ioapic_gsi0()
by Kyösti Mälkki (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Stefan Ott, Alexander Couzens, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55315 ) Change subject: drivers/generic/ioapic: Use register_new_ioapic_gsi0() ...................................................................... Patch Set 9: (1 comment) Patchset: PS8: > This doesn't compile for me (X200): […] Hmm.. you must have done a cherry-pick instead of checkout. -- To view, visit https://review.coreboot.org/c/coreboot/+/55315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b03d32fa16fb9eb8a035e58bb7e3e027904f076 Gerrit-Change-Number: 55315 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Nov 2022 06:47:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Ott <coreboot(a)desire.ch> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Add support to read CPU and PCH Trace Hub modes
by Sridhar Siricilla (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Subrata Banik, Paul Menzel, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64437 ) Change subject: soc/intel/common: Add support to read CPU and PCH Trace Hub modes ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Ack Reminder -- To view, visit https://review.coreboot.org/c/coreboot/+/64437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2 Gerrit-Change-Number: 64437 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 06:46:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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