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Change subject: drivers/ocp: add VPD processing framework
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/ocp/vpd/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68784/comment/611dfab9_50640a14
PS2, Line 3: smm-$(C
> Config VPD_SMM_SUPPORT is uploaded to CB:67092 for VPD access in SMM.
It's a bad idea if you just want boot time configuration. I suggest passing the configuration once, just like how it's done for passing the cbmemc buffer.
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Change subject: drivers/vpd, cpu/x86/smm: Add VPD support for SMM
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67092/comment/7b700590_d9ccc1ed
PS4, Line 9: The main purpose is to be able to dynamically configure system during
: SMM boot time via VPD.
It does way more than fulfill that purpose. The os could in principle also update the memory of that CBMEM region. Do you trust the SMM code enough that it will properly handle malformed input? It's not a safe thing to do so if your goal is to only have some boot time configuration, then you want a different mechanism than bloating the runtime. I suggest passing your configuration just like you pass the cbmemc buffer.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69493 )
Change subject: packeteer 6500
......................................................................
Patch Set 1:
(10 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69493/comment/574a262e_f7ad56c6
PS1, Line 7: packeteer 6500
> At coreboot, we prefer to start the subject line with a path, and to make sure we have a verb in the […]
It's a good idea to list what is tested and works, what does not work, and what is not tested.
https://review.coreboot.org/c/coreboot/+/69493/comment/b79052cc_3eb1e629
PS1, Line 8:
> Needs a developer's certificate of origin sign-off saying that this is code that you have the rights […]
You can amend the sign-off into your commit: `git commit -s --amend`
Patchset:
PS1:
> Hey, welcome to coreboot! You might want to look through some of the documentation: https://corebo […]
Welcome!
File src/arch/x86/pirq_routing.c:
https://review.coreboot.org/c/coreboot/+/69493/comment/4e3afdf3_76e19b4a
PS1, Line 143: if (link > 0x5f) {
: link -= 0x5f;
: }
> Split this int a separate patch and explain why its needed please.
+1
File src/cpu/intel/Kconfig:
https://review.coreboot.org/c/coreboot/+/69493/comment/640f823b_a956252e
PS1, Line 19: source "src/cpu/intel/socket_FC_PGA370/Kconfig"
> Please split all of the cpu/intel files into a separate commit.
Adding the socket can be its own commit
File src/mainboard/packeteer/6500/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/69493/comment/ea751cfc_1bcf7c76
PS1, Line 35: #include <acpi/dsdt_top.asl>
This should probably be the first include
https://review.coreboot.org/c/coreboot/+/69493/comment/4ce6082e_9f319f76
PS1, Line 89: Method(OSFL, 0){
:
: if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
:
: if(CondRefOf(\_OSI))
: {
: Store(1, OSVR) /* Assume some form of XP */
: if (\_OSI("Windows 2006")) /* Vista */
: {
: Store(2, OSVR)
: }
: } else {
: If(WCMP(\_OS,"Linux")) {
: Store(3, OSVR) /* Linux */
: } Else {
: Store(4, OSVR) /* Gotta be WinCE */
: }
: }
: Return(OSVR)
: }
Please use tabs for indentation. Also, do you think some of this could be factored out? It seems like some of this is common with asus/p2b
File src/mainboard/packeteer/6500/dsdt.asl2:
PS1:
Is this used?
File src/mainboard/packeteer/6500/irq_tables.c:
https://review.coreboot.org/c/coreboot/+/69493/comment/4ff9e3f9_4c166edf
PS1, Line 27: PIRQ_SIGNATURE, /* u32 signature */
> code indent should use tabs where possible
Please fix.
File src/mainboard/packeteer/6500/superio.asl:
https://review.coreboot.org/c/coreboot/+/69493/comment/9b254287_206d9065
PS1, Line 5: * expose the W83977TF/EF SuperIO and some of its functionality.
Is this correct? The mainboard seems to have a SMSC Super I/O
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Hello build bot (Jenkins), Nico Huber, Martin L Roth, Tristan Corrick, Angel Pons, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64218
to look at the new patch set (#5).
Change subject: superio/acpi/pnp_generic.asl: Add _PRS for each device
......................................................................
superio/acpi/pnp_generic.asl: Add _PRS for each device
Simply return the current resource settings in the _PRS method. This
means that coreboot has to correctly set up the resources on the
device. This won't result in any regression as without _PRS the ACPI
OS would not know what resources settings are valid, so it would never
use _SRS.
Change-Id: I2726714cbe076fc7c772c06883d8551400ff2baa
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
M src/mainboard/acer/g43t-am3/Kconfig
M src/mainboard/asrock/h81m-hds/Kconfig
M src/mainboard/asus/h61-series/Kconfig
M src/mainboard/asus/p5qpl-am/Kconfig
M src/mainboard/foxconn/d41s/Kconfig
M src/mainboard/foxconn/g41s-k/Kconfig
M src/mainboard/gigabyte/ga-d510ud/Kconfig
M src/mainboard/intel/dcp847ske/Kconfig
M src/mainboard/intel/dg41wv/Kconfig
M src/mainboard/intel/dg43gt/Kconfig
M src/mainboard/intel/emeraldlake2/Kconfig
M src/mainboard/supermicro/x10slm-f/Kconfig
M src/mainboard/supermicro/x9scl/Kconfig
M src/superio/acpi/pnp_generic.asl
15 files changed, 24 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/64218/5
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Change subject: drivers/ocp: add VPD processing framework
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/ocp/vpd/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68784/comment/b93bb3b9_eb3b3fd5
PS2, Line 3: smm-$(C
> > Arthur, didn't you have some patches to allow passing runtime-configurable settings to the SMI han […]
Config VPD_SMM_SUPPORT is uploaded to CB:67092 for VPD access in SMM.
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Change subject: mb/emulation/qemu: Move packed attribute
......................................................................
Patch Set 1: Code-Review+2
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