coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/brya: Disable the Package C-state demotion
by build bot (Jenkins) (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69614 ) Change subject: mb/google/brya: Disable the Package C-state demotion ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163725): https://review.coreboot.org/c/coreboot/+/69614/comment/9ac8d358_7d4c2427 PS1, Line 8: 'Packge' may be misspelled - perhaps 'Package'? -- To view, visit https://review.coreboot.org/c/coreboot/+/69614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad2f4601f0a5760c6099d7d2a757c7c460aaf53d Gerrit-Change-Number: 69614 Gerrit-PatchSet: 1 Gerrit-Owner: Shaik Sameeruddin <shaik.sameeruddin(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Tue, 15 Nov 2022 14:31:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: Disable the Package C-state demotion
by Shaik Sameeruddin (Code Review) 15 Nov '22

15 Nov '22

Shaik Sameeruddin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69614 ) Change subject: mb/google/brya: Disable the Package C-state demotion ...................................................................... mb/google/brya: Disable the Package C-state demotion Enabling the Packge C-state demotion for checking Power and Performance impact Signed-off-by: sameeruddin shaik <shaik.sameeruddin(a)intel.com> Change-Id: Iad2f4601f0a5760c6099d7d2a757c7c460aaf53d --- M src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/69614/1 diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb index c861c9b..447d51c 100644 --- a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb @@ -77,7 +77,7 @@ # FIXME: To be enabled in future based on PNP impact data. # Disable Package C-state demotion for brya baseboard. - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "0" # Intel Common SoC Config #+-------------------+---------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/69614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad2f4601f0a5760c6099d7d2a757c7c460aaf53d Gerrit-Change-Number: 69614 Gerrit-PatchSet: 1 Gerrit-Owner: Shaik Sameeruddin <shaik.sameeruddin(a)intel.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: Documentation/sbom: Add SBOM Documentation
by Nicholas Chin (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Patrick Rudolph, Richard Hughes, Maximilian Brune, Angel Pons. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68995 ) Change subject: Documentation/sbom: Add SBOM Documentation ...................................................................... Patch Set 8: (3 comments) File Documentation/sbom/sbom.md: https://review.coreboot.org/c/coreboot/+/68995/comment/3a8b4233_97c4c93c PS8, Line 94: 3. To build coreboot: Add `CONFIG_SBOM_[software-name]_PATH` to your defconfig pointing to your [software-name] generated File. Please reflow to 72 chars https://review.coreboot.org/c/coreboot/+/68995/comment/483f6e51_af439d50 PS8, Line 97: 1. Generate a SWID/CoSWID/uSWID File in either JSON, XML or CBOR Format as part of your software's build process. for example in form of a Makefile target. Same as above https://review.coreboot.org/c/coreboot/+/68995/comment/90bc95be_b3dbec99 PS8, Line 98: 2. Change src/sbom/Makefile.inc (in order to know where to find the CoSWID/SWID/uSWID File) as well as the Makefile in coreboot which builds said software. For example for GRUB2 that could mean to add a Makefile target in payloads/external/GRUB2/Makefile. Same as above -- To view, visit https://review.coreboot.org/c/coreboot/+/68995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fbcba60a0fbdbed9f662119ed7692c0a0fd30e Gerrit-Change-Number: 68995 Gerrit-PatchSet: 8 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Richard Hughes <richard(a)hughsie.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Richard Hughes <richard(a)hughsie.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Nov 2022 14:31:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd: commonize generation of the PIC/APIC mapping tables
by Felix Held (Code Review) 15 Nov '22

15 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68853 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd: commonize generation of the PIC/APIC mapping tables ...................................................................... soc/amd: commonize generation of the PIC/APIC mapping tables Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/birman/mainboard.c M src/mainboard/amd/chausie/mainboard.c M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/majolica/mainboard.c M src/mainboard/amd/mandolin/mainboard.c M src/mainboard/amd/pademelon/mainboard.c M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/skyrim/mainboard.c M src/mainboard/google/zork/mainboard.c M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/amd_pci_util.c 13 files changed, 97 insertions(+), 530 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index ca85684..a751126 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -9,7 +9,6 @@ #include <soc/southbridge.h> #include <soc/pci_devs.h> #include <soc/platform_descriptors.h> -#include <string.h> #include <types.h> #include <commonlib/helpers.h> #include <soc/amd/picasso/chip.h> @@ -20,17 +19,8 @@ /* TODO: recheck IRQ tables */ -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; - +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ static const struct fch_irq_routing fch_irq_map[] = { { PIRQ_A, 8, 16 }, { PIRQ_B, 10, 17 }, @@ -56,41 +46,12 @@ { PIRQ_MISC2, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - -static void pirq_setup(void) -{ - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; -} - static void program_display_sel_gpios(void) { int idx, port_type; @@ -125,14 +86,6 @@ mainboard_program_emmc_gpios(); } -static void mainboard_enable(struct device *dev) -{ - init_tables(); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/amd/birman/mainboard.c b/src/mainboard/amd/birman/mainboard.c index 28c289d..6a7343f 100644 --- a/src/mainboard/amd/birman/mainboard.c +++ b/src/mainboard/amd/birman/mainboard.c @@ -2,25 +2,15 @@ #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> -#include <console/console.h> #include <device/device.h> #include <soc/acpi.h> -#include <string.h> #include <types.h> #include "gpio.h" /* TODO: Update for birman */ -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ /* * This controls the device -> IRQ routing. @@ -61,54 +51,17 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - -static void pirq_setup(void) -{ - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; -} - static void mainboard_init(void *chip_info) { mainboard_program_gpios(); } -static void mainboard_enable(struct device *dev) -{ - init_tables(); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/amd/chausie/mainboard.c b/src/mainboard/amd/chausie/mainboard.c index 9515f24..17c9d78 100644 --- a/src/mainboard/amd/chausie/mainboard.c +++ b/src/mainboard/amd/chausie/mainboard.c @@ -2,23 +2,13 @@ #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> -#include <console/console.h> #include <device/device.h> #include <soc/acpi.h> -#include <string.h> #include <types.h> #include "gpio.h" -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ /* * This controls the device -> IRQ routing. @@ -59,54 +49,17 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - -static void pirq_setup(void) -{ - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; -} - static void mainboard_init(void *chip_info) { mainboard_program_gpios(); } -static void mainboard_enable(struct device *dev) -{ - init_tables(); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 0bbb208..ad95617 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -3,24 +3,13 @@ #include <device/device.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> -#include <console/console.h> #include <soc/gpio.h> #include <soc/southbridge.h> -#include <string.h> #include "gpio.h" -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; - +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ static const struct fch_irq_routing fch_irq_map[] = { { PIRQ_A, 3, 16 }, { PIRQ_B, 4, 17 }, @@ -53,42 +42,12 @@ { PIRQ_MISC2, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; -} - static void mainboard_init(void *chip_info) { size_t num_gpios; @@ -97,17 +56,6 @@ gpio_configure_pads(gpios, num_gpios); } -/************************************************* - * enable the dedicated function in gardenia board. - *************************************************/ -static void mainboard_enable(struct device *dev) -{ - init_tables(); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c index a5e2935..9dbd4e4 100644 --- a/src/mainboard/amd/majolica/mainboard.c +++ b/src/mainboard/amd/majolica/mainboard.c @@ -2,22 +2,12 @@ #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> -#include <console/console.h> #include <device/device.h> #include <soc/acpi.h> -#include <string.h> #include <types.h> -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ /* * This controls the device -> IRQ routing. @@ -59,53 +49,16 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - -static void pirq_setup(void) -{ - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; -} - static void mainboard_init(void *chip_info) { } -static void mainboard_enable(struct device *dev) -{ - init_tables(); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index 397179a..6a27514 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -7,7 +7,6 @@ #include <soc/cpu.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <string.h> #include <types.h> #include <commonlib/helpers.h> #include <soc/amd/picasso/chip.h> @@ -15,17 +14,8 @@ /* TODO: recheck IRQ tables */ -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; - +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ static const struct fch_irq_routing fch_irq_map[] = { { PIRQ_A, 8, 16 }, { PIRQ_B, 10, 17 }, @@ -51,41 +41,12 @@ { PIRQ_MISC2, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - -static void pirq_setup(void) -{ - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; -} - static void mainboard_init(void *chip_info) { struct soc_amd_picasso_config *cfg = config_of_soc(); @@ -102,14 +63,6 @@ mainboard_program_emmc_gpios(); } -static void mainboard_enable(struct device *dev) -{ - init_tables(); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/amd/pademelon/mainboard.c b/src/mainboard/amd/pademelon/mainboard.c index 9c55808..12f0443 100644 --- a/src/mainboard/amd/pademelon/mainboard.c +++ b/src/mainboard/amd/pademelon/mainboard.c @@ -3,25 +3,14 @@ #include <device/device.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> -#include <console/console.h> #include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> -#include <string.h> #include "gpio.h" -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; - +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ static const struct fch_irq_routing fch_irq_map[] = { { PIRQ_A, 3, 16 }, { PIRQ_B, 4, 17 }, @@ -54,35 +43,12 @@ { PIRQ_MISC2, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - /* * This table defines the index into the picr/intr_data tables for each * device. Any enabled device and slot that uses hardware interrupts should @@ -113,8 +79,6 @@ { pirq_data_ptr = mainboard_pirq_data; pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; } static void mainboard_init(void *chip_info) @@ -130,7 +94,6 @@ *************************************************/ static void mainboard_enable(struct device *dev) { - init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 8deb2ac..a7eab08 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -12,7 +12,6 @@ #include <gpio.h> #include <soc/acpi.h> #include <variant/ec.h> -#include <string.h> #define BACKLIGHT_GPIO GPIO_129 #define WWAN_AUX_RST_GPIO GPIO_18 @@ -23,16 +22,8 @@ #define METHOD_MAINBOARD_PTS "\\_SB.MPTS" #define METHOD_MAINBOARD_S0X "\\_SB.MS0X" -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ /* * This controls the device -> IRQ routing. @@ -74,41 +65,12 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - -static void pirq_setup(void) -{ - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; -} - static void mainboard_configure_gpios(void) { size_t base_num_gpios, override_num_gpios; @@ -219,10 +181,6 @@ dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; - init_tables(); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); - /* TODO: b/184678786 - Move into espi_config */ /* Unmask eSPI IRQ 1 (Keyboard) */ pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 3433f8b..9cbfd4b 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -18,17 +18,8 @@ #include <variant/ec.h> #include <variant/thermal.h> -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; - +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ static const struct fch_irq_routing fch_irq_map[] = { { PIRQ_A, 3, 16 }, { PIRQ_B, 4, 17 }, @@ -61,35 +52,12 @@ { PIRQ_MISC2, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - /* * This table defines the index into the picr/intr_data tables for each * device. Any enabled device and slot that uses hardware interrupts should @@ -117,8 +85,6 @@ { pirq_data_ptr = mainboard_pirq_data; pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; } void __weak variant_devtree_update(void) @@ -165,7 +131,6 @@ *************************************************/ static void mainboard_enable(struct device *dev) { - init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index ca3c9aa..7708488 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -6,19 +6,10 @@ #include <console/console.h> #include <device/device.h> #include <soc/acpi.h> -#include <string.h> #include <variant/ec.h> -/* - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ /* * This controls the device -> IRQ routing. @@ -60,41 +51,12 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - -static void pirq_setup(void) -{ - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; -} - static void mainboard_configure_gpios(void) { size_t base_num_gpios, override_num_gpios; @@ -117,10 +79,6 @@ { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - init_tables(); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); - /* TODO: b/184678786 - Move into espi_config */ /* Unmask eSPI IRQ 1 (Keyboard) */ pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index aaa2548..90c74d7 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <string.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> @@ -31,16 +30,8 @@ #define METHOD_MAINBOARD_WAK "\\_SB.MWAK" #define METHOD_MAINBOARD_PTS "\\_SB.MPTS" -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - */ -static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ /* * This controls the device -> IRQ routing. @@ -78,42 +69,12 @@ { PIRQ_MISC2, 0x00, 0x00 }, }; -static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) { *length = ARRAY_SIZE(fch_irq_map); return fch_irq_map; } -static void init_tables(void) -{ - const struct fch_irq_routing *mb_irq_map; - size_t mb_fch_irq_mapping_table_size; - size_t i; - - mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); - - memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); - memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - - for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { - if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { - printk(BIOS_WARNING, - "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", - mb_irq_map[i].intr_index, i); - continue; - } - fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; - fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; - } -} - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = fch_apic_routing; - picr_data_ptr = fch_pic_routing; -} - static void mainboard_configure_gpios(void) { size_t base_num_gpios, override_num_gpios; @@ -205,12 +166,7 @@ *************************************************/ static void mainboard_enable(struct device *dev) { - init_tables(); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); - dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; - } static void mainboard_final(void *chip_info) diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index c766d50..f862bf9 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -19,6 +19,8 @@ uint8_t apic_irq_num; }; +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length); + struct pirq_struct { u8 devfn; u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ @@ -31,8 +33,6 @@ extern const struct pirq_struct *pirq_data_ptr; extern u32 pirq_data_size; -extern const u8 *intr_data_ptr; -extern const u8 *picr_data_ptr; u8 read_pci_int_idx(u8 index, int mode); void write_pci_int_idx(u8 index, int mode, u8 data); diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c index d665a81..ecc0498 100644 --- a/src/soc/amd/common/block/pci/amd_pci_util.c +++ b/src/soc/amd/common/block/pci/amd_pci_util.c @@ -7,11 +7,21 @@ #include <amdblocks/amd_pci_util.h> #include <pc80/i8259.h> #include <soc/amd_pci_int_defs.h> +#include <string.h> + +/* + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + */ +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; const struct pirq_struct *pirq_data_ptr; u32 pirq_data_size; -const u8 *intr_data_ptr; -const u8 *picr_data_ptr; /* * Read the FCH PCI_INTR registers 0xC00/0xC01 at a @@ -33,6 +43,29 @@ outb(data, PCI_INTR_DATA); } +static void init_fch_irq_map_tables(void) +{ + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; + } +} + /* * Write the FCH PCI_INTR registers 0xC00/0xC01 with values * given in global variables intr_data and picr_data. @@ -44,13 +77,13 @@ size_t i, limit; const struct irq_idx_name *idx_name; + init_fch_irq_map_tables(); + idx_name = sb_get_apic_reg_association(&limit); - if (picr_data_ptr == NULL || intr_data_ptr == NULL || - idx_name == NULL) { + if (idx_name == NULL) { printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01" " registers because\n" - "'mainboard_picr_data' or 'mainboard_intr_data'" - " or 'irq_association'\ntables are NULL\n"); + " 'irq_association'\ntables is NULL\n"); return; } @@ -67,11 +100,11 @@ */ for (i = 0 ; i < limit; i++) { byte = idx_name[i].index; - write_pci_int_idx(byte, 0, (u8)picr_data_ptr[byte]); + write_pci_int_idx(byte, 0, fch_pic_routing[byte]); printk(BIOS_DEBUG, "0x%02X\t\t%-20s 0x%02X\t", byte, idx_name[i].name, read_pci_int_idx(byte, 0)); - write_pci_int_idx(byte, 1, (u8)intr_data_ptr[byte]); + write_pci_int_idx(byte, 1, fch_apic_routing[byte]); printk(BIOS_DEBUG, "0x%02X\n", read_pci_int_idx(byte, 1)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/68853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Gerrit-Change-Number: 68853 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/soc/intel/xeon_sp/ras/hest.c: fix HEST table length
by Jeff Li (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Jeff Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69500 ) Change subject: src/soc/intel/xeon_sp/ras/hest.c: fix HEST table length ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/xeon_sp/ras/hest.c: https://review.coreboot.org/c/coreboot/+/69500/comment/641aed64_e57c3bba PS3, Line 62: void *current; : current = (void *)(hest); : void *next = current; : next = hest + 1; > > Thank you for pointing out this problem of arithmetics on pointers to void. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4780785bac782aa966def3f042f365a1ead9d9d8 Gerrit-Change-Number: 69500 Gerrit-PatchSet: 7 Gerrit-Owner: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 15 Nov 2022 14:27:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/morgana/Kconfig: Remove TODO after review
by Fred Reitberger (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69275 ) Change subject: soc/amd/morgana/Kconfig: Remove TODO after review ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > gerrit shows me a merge conflict on this file Looks like I had made the same changes in multiple patches, creating the merge conflict. I just rebased it off of master, so it should be clean now -- To view, visit https://review.coreboot.org/c/coreboot/+/69275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3 Gerrit-Change-Number: 69275 Gerrit-PatchSet: 4 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 15 Nov 2022 14:00:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/morgana/Kconfig: Remove TODO after review
by Fred Reitberger (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Matt DeVillier, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69275 to look at the new patch set (#4). Change subject: soc/amd/morgana/Kconfig: Remove TODO after review ...................................................................... soc/amd/morgana/Kconfig: Remove TODO after review Remove TODO comments after reviwing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3 --- M src/soc/amd/morgana/Kconfig M src/soc/amd/morgana/uart.c 2 files changed, 30 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/69275/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3 Gerrit-Change-Number: 69275 Gerrit-PatchSet: 4 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/picasso: Add support for 64bit builds
by Fred Reitberger (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Arthur Heymans. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63727 ) Change subject: soc/amd/picasso: Add support for 64bit builds ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b Gerrit-Change-Number: 63727 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 15 Nov 2022 13:43:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: transition full control over PM Timer from FSP ...
by Kapil Porwal (Code Review) 15 Nov '22

15 Nov '22

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69613 ) Change subject: soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot ...................................................................... soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Port of commit 0e905801f8ff ("soc/intel: transition full control over PM Timer from FSP to coreboot"). BUG=none TEST=Boot to OS on google/rex. Excerpt from google/rex coreboot log: [SPEW ] EnableTcoTimer = 1 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027 --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/69613/1 diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 4fe2f63..1323c06 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -349,6 +349,19 @@ s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); } +static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_meteorlake_config *config) +{ + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + s_cfg->EnableTcoTimer = 1; +} + static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) { @@ -429,6 +442,7 @@ fill_fsps_vmd_params, fill_fsps_tbt_params, fill_fsps_8254_params, + fill_fsps_pm_timer_params, fill_fsps_pcie_params, fill_fsps_misc_power_params, fill_fsps_ufs_params, -- To view, visit https://review.coreboot.org/c/coreboot/+/69613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027 Gerrit-Change-Number: 69613 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/prodrive/atlas: add unique DIMM locators in smbios type17
by David Milosevic (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Christian Walter, Angel Pons, Lean Sheng Tan. Hello build bot (Jenkins), Christian Walter, Angel Pons, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68632 to look at the new patch set (#4). Change subject: mb/prodrive/atlas: add unique DIMM locators in smbios type17 ...................................................................... mb/prodrive/atlas: add unique DIMM locators in smbios type17 This patch adds unique device-locators, bank-locators and asset-tags to the smbios type17 tables by making use of a DIMMs controller-ID. This way we avoid name clashes when, for example, two DIMMs share the same channel-ID and DIMM-ID but have a distinct controller-ID. Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: I8aef79faa43f2475485f581c675ee152e580f678 --- M src/mainboard/prodrive/atlas/mainboard.c 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/68632/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8aef79faa43f2475485f581c675ee152e580f678 Gerrit-Change-Number: 68632 Gerrit-PatchSet: 4 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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