coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: mb/google/geralt: Enable RTC for eventlog timestamps
by Felix Held (Code Review) 15 Nov '22

15 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69432 ) Change subject: mb/google/geralt: Enable RTC for eventlog timestamps ...................................................................... mb/google/geralt: Enable RTC for eventlog timestamps Without RTC, the timestamps in the eventlog are currently all '2000-00-00 00:00:00'. Enable RTC to get the correct timestamps. localhost ~ # head /var/log/eventlog.txt 0 | 2022-10-15 22:59:38 | Log area cleared | 4088 1 | 2022-10-15 22:59:38 | Memory Cache Update | Normal | Success 2 | 2022-10-15 22:59:45 | System boot | 0 3 | 2022-10-15 22:59:46 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown localhost ~ # localhost ~ # date Sun Oct 16 01:42:59 PDT 2022 localhost ~ # BUG=b:233720142 TEST=check the timestamp field in /var/log/eventlog.txt Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69432 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/geralt/Kconfig M src/soc/mediatek/mt8188/Makefile.inc 2 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig index a911cb8..40a0f89 100644 --- a/src/mainboard/google/geralt/Kconfig +++ b/src/mainboard/google/geralt/Kconfig @@ -30,6 +30,7 @@ select TPM_GOOGLE_TI50 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select RTC config MAINBOARD_DIR string diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 52fc861..13fea31 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif_spi.c pmif_spi.c +ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c -- To view, visit https://review.coreboot.org/c/coreboot/+/69432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a Gerrit-Change-Number: 69432 Gerrit-PatchSet: 5 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/google/brya/var/marasov: Add memory config for marasov
by Felix Held (Code Review) 15 Nov '22

15 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69149 ) Change subject: mb/google/brya/var/marasov: Add memory config for marasov ...................................................................... mb/google/brya/var/marasov: Add memory config for marasov Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:254365935 BRANCH=None TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69149 Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- A src/mainboard/google/brya/variants/marasov/Makefile.inc A src/mainboard/google/brya/variants/marasov/memory.c 2 files changed, 135 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frank Chu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/marasov/Makefile.inc b/src/mainboard/google/brya/variants/marasov/Makefile.inc new file mode 100644 index 0000000..c44e4f0 --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/Makefile.inc @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/marasov/memory.c b/src/mainboard/google/brya/variants/marasov/memory.c new file mode 100644 index 0000000..fb7c748 --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/memory.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 3, 2, 1, 6, 4, 5, 7 }, + .dq1 = { 14, 12, 13, 15, 11, 8, 10, 9 }, + }, + .ddr1 = { + .dq0 = { 1, 0, 2, 3, 6, 4, 7, 5 }, + .dq1 = { 15, 13, 12, 14, 8, 11, 10, 9 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 7, 6, 4, 5 }, + .dq1 = { 14, 12, 13, 15, 8, 9, 10, 11 }, + }, + .ddr3 = { + .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5 }, + .dq1 = { 13, 15, 12, 14, 8, 9, 10, 11 }, + }, + .ddr4 = { + .dq0 = { 2, 3, 0, 1, 6, 5, 7, 4 }, + .dq1 = { 14, 12, 13, 15, 8, 10, 9, 11 }, + }, + .ddr5 = { + .dq0 = { 1, 0, 3, 2, 6, 4, 7, 5 }, + .dq1 = { 15, 13, 12, 14, 11, 8, 10, 9 }, + }, + .ddr6 = { + .dq0 = { 0, 3, 1, 2, 4, 5, 7, 6 }, + .dq1 = { 15, 13, 14, 12, 9, 10, 8, 11 }, + }, + .ddr7 = { + .dq0 = { 0, 3, 2, 1, 5, 6, 7, 4 }, + .dq1 = { 14, 10, 13, 12, 8, 11, 15, 9 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E11 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + */ + gpio_t spd_gpios[] = { + GPP_E11, + GPP_E2, + GPP_E1, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool __weak variant_is_half_populated(void) +{ + /* + * Ideally half_populated is used in platforms with multiple channels to + * enable only one half of the channel. Alder Lake N has single channel, + * and it would require for new structures to be defined in meminit block + * driver for LPx memory configurations. In order to avoid adding new + * structures, set half_populated to true. This has the same effect as + * having single channel with 64-bit width. + */ + /* GPIO_MEM_CH_SEL GPP_E13 */ + return gpio_get(GPP_E13); +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4 Gerrit-Change-Number: 69149 Gerrit-PatchSet: 14 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/clevo/cml-u: Fix CMOS options
by Felix Held (Code Review) 15 Nov '22

15 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69521 ) Change subject: mb/clevo/cml-u: Fix CMOS options ...................................................................... mb/clevo/cml-u: Fix CMOS options The `hyper_threading` CMOS option was hooked up to the wrong enumeration and lacked a default value in `cmos.default`. Thus, use the correct enum for the `hyper_threading` option, remove the now-unused "backwards" enum and provide a default value in `cmos.default`. Change-Id: I56b0320f9210cde8ff58db176d2b7d2207c98aa9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69521 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/cmos.default M src/mainboard/clevo/cml-u/cmos.layout 2 files changed, 22 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, approved Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/cmos.default b/src/mainboard/clevo/cml-u/cmos.default index a20f1b1..098bfa6 100644 --- a/src/mainboard/clevo/cml-u/cmos.default +++ b/src/mainboard/clevo/cml-u/cmos.default @@ -1,5 +1,6 @@ boot_option=Fallback debug_level=Debug +hyper_threading=Enable power_on_after_fail=Disable # EC options diff --git a/src/mainboard/clevo/cml-u/cmos.layout b/src/mainboard/clevo/cml-u/cmos.layout index 391deb1..8350704 100644 --- a/src/mainboard/clevo/cml-u/cmos.layout +++ b/src/mainboard/clevo/cml-u/cmos.layout @@ -17,7 +17,7 @@ # ----------------------------------------------------------------- # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 1 hyper_threading # ----------------------------------------------------------------- # coreboot config options: southbridge @@ -52,8 +52,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency -- To view, visit https://review.coreboot.org/c/coreboot/+/69521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56b0320f9210cde8ff58db176d2b7d2207c98aa9 Gerrit-Change-Number: 69521 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
by Lean Sheng Tan (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: weidong.wd(a)bytedance.com, Angel Pons, Arthur Heymans, TangYiwei, Andrey Petrov, Sean Rhodes, Tarun Tuli, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Tim Wawrzynczak, David Milosevic, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68525 ) Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Gerrit-Change-Number: 68525 Gerrit-PatchSet: 7 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: weidong.wd(a)bytedance.com Gerrit-Attention: weidong.wd(a)bytedance.com Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 15 Nov 2022 13:08:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/rex: Add `disable_gpio_export_in_crs` for rex
by Subrata Banik (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69612 ) Change subject: mb/google/rex: Add `disable_gpio_export_in_crs` for rex ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: @Ivy, can you please check if Touch Screen is functional with this CL. I'm still on Brya Panel (w/o touch) -- To view, visit https://review.coreboot.org/c/coreboot/+/69612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I578a60eff27f94d6dc94b900604bc7560337d60b Gerrit-Change-Number: 69612 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 15 Nov 2022 13:03:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/rex: Add `disable_gpio_export_in_crs` for rex
by Subrata Banik (Code Review) 15 Nov '22

15 Nov '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69612 ) Change subject: mb/google/rex: Add `disable_gpio_export_in_crs` for rex ...................................................................... mb/google/rex: Add `disable_gpio_export_in_crs` for rex None of the touchscreens used in the rex program should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS. BUG=none TEST=Able to build and boot Google, Rex platform. Without this patch: [ERROR] I2C: 00:10: Exposing GPIOs in Power Resource and _CRS With this patch: None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I578a60eff27f94d6dc94b900604bc7560337d60b --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/69612/1 diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index a7f5a95..f3b0fab 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -357,6 +357,7 @@ register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)" register "generic.stop_off_delay_ms" = "2" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I578a60eff27f94d6dc94b900604bc7560337d60b Gerrit-Change-Number: 69612 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: WIP:soc/amd/morgana: Move PSP FWs to 0x20000
by Felix Held (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69470 ) Change subject: WIP:soc/amd/morgana: Move PSP FWs to 0x20000 ...................................................................... Patch Set 2: (2 comments) File src/mainboard/amd/birman/Kconfig: https://review.coreboot.org/c/coreboot/+/69470/comment/fd29e024_f694d346 PS2, Line 31: default 5 for chromeos we didn't use the first possible efs location (which is the soc default) so that it resides in the RO partition. for the non-chrome configuration we just use the default from the soc's kconfig File src/mainboard/amd/birman/board.fmd: https://review.coreboot.org/c/coreboot/+/69470/comment/7dc0ca23_40ad973f PS2, Line 5: FMAP 3K won't this result in a non erase block aligned cbfs? -- To view, visit https://review.coreboot.org/c/coreboot/+/69470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b1c7f9a7488a4d5ef94f21099692a23c3f8d27c Gerrit-Change-Number: 69470 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Nov 2022 12:40:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/cmn/block/acpi: enable BERT table without crashlog
by Shuming Chu (Shuming) (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Jonathan Zhang. Shuming Chu (Shuming) has uploaded a new patch set (#3) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/68878 ) Change subject: soc/intel/cmn/block/acpi: enable BERT table without crashlog ...................................................................... soc/intel/cmn/block/acpi: enable BERT table without crashlog Besides crashlog, there's also other errors such as MCA error, which should be recorded in BERT table. With current code, BERT table is not generated if crashlog is not enabled. Add if statement for SOC_INTEL_CRASHLOG so that MCA error can be recorded in BERT table when crashlog is not supported. For some server mainboard, crashlog is supported through BMC instead of host firmware. Also check if BERT region is generated when crashlog is not enabled. Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> --- M src/soc/intel/common/block/acpi/acpi_bert.c 1 file changed, 39 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/68878/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f Gerrit-Change-Number: 68878 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: soc/amd/morgana/Kconfig: Remove TODO after review
by Felix Held (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69275 ) Change subject: soc/amd/morgana/Kconfig: Remove TODO after review ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: gerrit shows me a merge conflict on this file -- To view, visit https://review.coreboot.org/c/coreboot/+/69275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3 Gerrit-Change-Number: 69275 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Nov 2022 12:05:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: cpu/x86/smm: Enable setting SMM console log level from mainboard
by Johnny Lin (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Marc Jones, Martin L Roth, Patrick Rudolph, Rocky Phagura, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang, Kyösti Mälkki. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49460 ) Change subject: cpu/x86/smm: Enable setting SMM console log level from mainboard ...................................................................... Patch Set 23: (1 comment) Patchset: PS23: > Build failure was due to poor configuration on a new builder. Added it to the queue again. Should I do something to trigger the build again? -- To view, visit https://review.coreboot.org/c/coreboot/+/49460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Gerrit-Change-Number: 49460 Gerrit-PatchSet: 23 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Nov 2022 12:03:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022