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Change subject: soc/amd/common: Don't set Wstack-usage option for clang builds
......................................................................
Patch Set 1: -Code-Review
(1 comment)
Patchset:
PS1:
pulling back my +2 until Jenkins is happy
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Change subject: soc/amd/common: Don't set Wstack-usage option for clang builds
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common: Don't set Wstack-usage option for clang builds
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
It looks like a similar flag for clang is `-Wframe-larger-than=`
gcc has that flag too, but it is less conservative than `-Wstack-usage=`, so it's probably not as good at catching things.
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69662 )
Change subject: soc/amd/common: Don't set Wstack-usage option for clang builds
......................................................................
soc/amd/common: Don't set Wstack-usage option for clang builds
Clang doesn't understand this option. It's currently blowing up builds.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I7d8b9c26d3fc861615a8553332ed1070974b751b
---
M src/soc/amd/common/psp_verstage/Makefile.inc
1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/69662/1
diff --git a/src/soc/amd/common/psp_verstage/Makefile.inc b/src/soc/amd/common/psp_verstage/Makefile.inc
index fb82ef4..489ac51 100644
--- a/src/soc/amd/common/psp_verstage/Makefile.inc
+++ b/src/soc/amd/common/psp_verstage/Makefile.inc
@@ -4,8 +4,10 @@
verstage-generic-ccopts += -D__USER_SPACE__
CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/
+ifeq ($(CONFIG_COMPILER_GCC),y)
# This size should match the size in the linker script.
CFLAGS_arm += -Wstack-usage=40960
+endif
verstage-y += boot_dev.c
verstage-y += delay.c
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69541 )
Change subject: mb/google/nissa: Add SD_BOOT fw_config
......................................................................
mb/google/nissa: Add SD_BOOT fw_config
Some nissa devices want to disable boot from SD card. Since nissa has a
single shared depthcharge target, add a program-wide fw_config to allow
disabling it.
BUG=b:253003881
TEST=With depthcharge change, set SD_BOOT_DISABLE on nivviks and check
SD card is not initialised in depthcharge.
Change-Id: I1a3a533e4e74e48d9ce4a9678b812cb62ce2066b
Signed-off-by: Reka Norman <rekanorman(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69541
Reviewed-by: Kangheui Won <khwon(a)chromium.org>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
1 file changed, 26 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kangheui Won: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index d002db6..24b5b70 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -1,4 +1,8 @@
fw_config
+ field SD_BOOT 29
+ option SD_BOOT_ENABLE 0
+ option SD_BOOT_DISABLE 1
+ end
field STORAGE 30 31
option STORAGE_EMMC 0
option STORAGE_NVME 1
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69162 )
Change subject: security/tpm: support compiling in multiple TPM drivers
......................................................................
Patch Set 7:
(2 comments)
File src/security/tpm/tis.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163730):
https://review.coreboot.org/c/coreboot/+/69162/comment/94f49c2b_5dcb5b55
PS7, Line 110: #define __tis_driver __attribute__((used, section(".rodata.tis_driver")))
Prefer __used over __attribute__((used))
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163730):
https://review.coreboot.org/c/coreboot/+/69162/comment/9808b74f_ec781573
PS7, Line 110: #define __tis_driver __attribute__((used, section(".rodata.tis_driver")))
Prefer __section(".rodata.tis_driver") over __attribute__((section(".rodata.tis_driver")))
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Hello Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69162
to look at the new patch set (#7).
Change subject: security/tpm: support compiling in multiple TPM drivers
......................................................................
security/tpm: support compiling in multiple TPM drivers
Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually
exclusive.
Making probe functions static and always using them uncovered that
bootblock stage included TPM driver which it didn't use. This is why
Makefile.inc files were updated to replace `all-*` with
romstage, ramstage and verstage.
Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/drivers/crb/Makefile.inc
M src/drivers/crb/tis.c
M src/drivers/i2c/tpm/Makefile.inc
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/drivers/pc80/tpm/Makefile.inc
M src/drivers/pc80/tpm/tis.c
M src/drivers/spi/tpm/Makefile.inc
M src/drivers/spi/tpm/tis.c
M src/lib/program.ld
M src/security/tpm/Kconfig
M src/security/tpm/tis.h
M src/security/tpm/tss/tss.c
M src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld
14 files changed, 99 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/69162/7
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