coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/emulation/qemu-q35: Split smm_close() and smm_lock()
by Kyösti Mälkki (Code Review) 15 Nov '22

15 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69667 ) Change subject: mb/emulation/qemu-q35: Split smm_close() and smm_lock() ...................................................................... mb/emulation/qemu-q35: Split smm_close() and smm_lock() Change-Id: I6d8efe783e6cc5413c3fd0583574a075a2c3876b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/cpu/intel/smm_reloc.h M src/mainboard/emulation/qemu-q35/cpu.c M src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 37 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/69667/1 diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 3d95efc..6b1a525 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -36,7 +36,8 @@ /* These helpers are for performing SMM relocation. */ void northbridge_write_smram(u8 smram); -void smm_open_aseg(void); +void smm_close(void); +void smm_open(void); void smm_lock(void); void smm_relocate(void); diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index 58b1fa5..c57ec50 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -18,8 +18,7 @@ smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - if (CONFIG(SMM_ASEG)) - smm_open_aseg(); + smm_open(); /* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */ *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); @@ -77,6 +76,9 @@ static void post_mp_init(void) { + /* Limit access to SMRAM to SMM module. */ + smm_close(); + /* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */ global_smi_enable(); diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index 3465613..3f3ced2 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -78,6 +78,26 @@ printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB); } +void smm_open(void) +{ + /* Set D_OPEN */ + if (CONFIG(SMM_ASEG)) + pci_write_config8(HOST_BRIDGE, SMRAMC, D_OPEN | G_SMRAME | C_BASE_SEG); + + if (CONFIG(SMM_TSEG)) + pci_and_config8(HOST_BRIDGE, ESMRAMC, ~T_EN); +} + +void smm_close(void) +{ + /* Clear D_OPEN */ + if (CONFIG(SMM_ASEG)) + pci_write_config8(HOST_BRIDGE, SMRAMC, G_SMRAME | C_BASE_SEG); + + if (CONFIG(SMM_TSEG)) + pci_or_config8(HOST_BRIDGE, ESMRAMC, T_EN); +} + void smm_lock(void) { /* @@ -87,13 +107,5 @@ */ printk(BIOS_DEBUG, "Locking SMM.\n"); - if (CONFIG(SMM_TSEG)) - pci_or_config8(HOST_BRIDGE, ESMRAMC, T_EN); - - pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); -} - -void smm_open_aseg(void) -{ - pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, G_SMRAME | C_BASE_SEG | D_OPEN); + pci_write_config8(HOST_BRIDGE, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d8efe783e6cc5413c3fd0583574a075a2c3876b Gerrit-Change-Number: 69667 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/emulation/qemu-q35: Release TSEG reserve with SMM_ASEG
by Kyösti Mälkki (Code Review) 15 Nov '22

15 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69666 ) Change subject: mb/emulation/qemu-q35: Release TSEG reserve with SMM_ASEG ...................................................................... mb/emulation/qemu-q35: Release TSEG reserve with SMM_ASEG If TSEG is not enabled, smm_region() should not reserve the region, so add a test for T_EN flag in ESMRAMC. For the SMM_ASEG case this moves CBMEM immediately below top-of-ram. Change-Id: I2da4b846d0767afe00e98fdee375914c1875ddf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/emulation/qemu-q35/memmap.c 1 file changed, 40 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/69666/1 diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index e73e0df..3465613 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -47,24 +47,33 @@ #define TSEG_SZ_MASK (3 << 1) #define H_SMRAME (1 << 7) +/* Decodes TSEG region size to bytes. */ +static size_t decode_tseg_size(u8 esmramc) +{ + /* If we intent to enable TSEG, fake it always enabled. */ + if (CONFIG(SMM_TSEG)) + esmramc |= T_EN; + + if (!(esmramc & T_EN)) + return 0; + + switch ((esmramc & TSEG_SZ_MASK) >> 1) { + case 0: + return 1 * MiB; + case 1: + return 2 * MiB; + case 2: + return 8 * MiB; + default: + return pci_read_config16(HOST_BRIDGE, EXT_TSEG_MBYTES) * MiB; + } +} + void smm_region(uintptr_t *start, size_t *size) { uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); - switch ((esmramc & TSEG_SZ_MASK) >> 1) { - case 0: - *size = 1 * MiB; - break; - case 1: - *size = 2 * MiB; - break; - case 2: - *size = 8 * MiB; - break; - default: - *size = pci_read_config16(HOST_BRIDGE, EXT_TSEG_MBYTES) * MiB; - } - + *size = decode_tseg_size(esmramc); *start = qemu_get_memory_size() * KiB - *size; printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB); } @@ -79,7 +88,8 @@ printk(BIOS_DEBUG, "Locking SMM.\n"); if (CONFIG(SMM_TSEG)) - pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN); + pci_or_config8(HOST_BRIDGE, ESMRAMC, T_EN); + pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2da4b846d0767afe00e98fdee375914c1875ddf5 Gerrit-Change-Number: 69666 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cpu/x86/smm: Use common SMM_ASEG region
by Kyösti Mälkki (Code Review) 15 Nov '22

15 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69665 ) Change subject: cpu/x86/smm: Use common SMM_ASEG region ...................................................................... cpu/x86/smm: Use common SMM_ASEG region Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/Makefile.inc M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/tseg_region.c M src/include/cpu/x86/smm.h M src/mainboard/emulation/qemu-q35/cpu.c 5 files changed, 25 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/69665/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index da93827..327b6c6 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -29,14 +29,10 @@ smm-y += save_state.c -ifeq ($(CONFIG_SMM_TSEG),y) - ramstage-y += tseg_region.c romstage-y += tseg_region.c postcar-y += tseg_region.c -endif - ifeq ($(CONFIG_PARALLEL_MP),y) smmstub-y += smm_stub.S diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6f334a2..6924f08 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -409,11 +409,6 @@ int smm_load_module(const uintptr_t smram_base, const size_t smram_size, struct smm_loader_params *params) { - if (CONFIG(SMM_ASEG) && (smram_base != SMM_BASE || smram_size != SMM_CODE_SEGMENT_SIZE)) { - printk(BIOS_ERR, "SMM base & size are 0x%lx, 0x%zx, but must be 0x%x, 0x%x\n", - smram_base, smram_size, SMM_BASE, SMM_CODE_SEGMENT_SIZE); - return -1; - } /* * Place in .bss to reduce stack usage. * TODO: once CPU_INFO_V2 is used everywhere, use smaller stack for APs and move diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index f6aecd0..413d5fc 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -26,7 +26,12 @@ const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&sub_base, &sub_size); + if (CONFIG(SMM_TSEG)) + smm_region(&sub_base, &sub_size); + else if (CONFIG(SMM_ASEG)) + aseg_region(&sub_base, &sub_size); + else + return -1; ASSERT(IS_ALIGNED(sub_base, sub_size)); ASSERT(sub_size > (cache_size + ied_size)); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b6d778b..7283a6b 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -165,6 +165,12 @@ */ void smm_region(uintptr_t *start, size_t *size); +static inline void aseg_region(uintptr_t *start, size_t *size) +{ + *start = SMM_BASE; + *size = SMM_DEFAULT_SIZE; /* SMM_CODE_SEGMENT_SIZE ? */ +} + enum { /* SMM handler area. */ SMM_SUBREGION_HANDLER, diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index c84b756..58b1fa5 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/helpers.h> #include <console/console.h> #include <cpu/amd/amd64_save_state.h> #include <cpu/intel/smm_reloc.h> @@ -15,14 +16,10 @@ { printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - if (CONFIG(SMM_TSEG)) - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - if (CONFIG(SMM_ASEG)) { + if (CONFIG(SMM_ASEG)) smm_open_aseg(); - *perm_smbase = 0xa0000; - *perm_smsize = 0x10000; - } /* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */ *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -- To view, visit https://review.coreboot.org/c/coreboot/+/69665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48 Gerrit-Change-Number: 69665 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
by Kyösti Mälkki (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Angel Pons, Kyösti Mälkki, Patrick Rudolph, Elyes Haouas. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61517 to look at the new patch set (#4). Change subject: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG ...................................................................... [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occuring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f2x/model_f2x_init.c A src/cpu/intel/model_f2x/mp_init.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c A src/southbridge/intel/i82801dx/smihandler.c 16 files changed, 258 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/61517/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Gerrit-Change-Number: 61517 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by Raul Rangel (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Jason Nien, EricKY Cheng, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Tim Van Patten, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 44: (3 comments) File src/soc/amd/common/acpi/DTTS.asl: PS42: Please make the filename lowercase. https://review.coreboot.org/c/coreboot/+/68471/comment/2fe14aef_ae50f89e PS42, Line 13: nit: trailing space https://review.coreboot.org/c/coreboot/+/68471/comment/12252843_d15ec5be PS42, Line 42: 123 These values are system specific. We should make these parameters in the device tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 44 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 15 Nov 2022 22:07:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
by Raul Rangel (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Jason Glenesk, EricKY Cheng, Matt DeVillier, Nelson Ye, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68470 ) Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib ...................................................................... Patch Set 21: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 Gerrit-Change-Number: 68470 Gerrit-PatchSet: 21 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 15 Nov 2022 22:00:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config
by Raul Rangel (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Martin Roth, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68942 ) Change subject: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/skyrim/Kconfig: https://review.coreboot.org/c/coreboot/+/68942/comment/5da0e139_e9d3b9c2 PS8, Line 146: FEATURE_DYNAMIC_DPTC > This is the CL before the others on the relation chain and only define but not enable. […] If this CL was merged into another one, then I would abandon this CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/68942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3db70c151f962184e0475a8d11a51568f4b8ced3 Gerrit-Change-Number: 68942 Gerrit-PatchSet: 8 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Tue, 15 Nov 2022 21:59:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/starlabs/starbook: Add Alder Lake StarBook Mk VI variant
by Sean Rhodes (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons, Ben McMillen, Elyes Haouas. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65785 ) Change subject: mb/starlabs/starbook: Add Alder Lake StarBook Mk VI variant ...................................................................... Patch Set 28: (1 comment) File src/mainboard/starlabs/starbook/variants/adl/hda_verb.c: https://review.coreboot.org/c/coreboot/+/65785/comment/678240b3_decdbb08 PS26, Line 71: u32 > It's just that Elyes wants you to include the header. […] Gotcha, thanks and done. -- To view, visit https://review.coreboot.org/c/coreboot/+/65785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc0c265a88b19cf9e89cc8ab3e8db9abd8cf8409 Gerrit-Change-Number: 65785 Gerrit-PatchSet: 28 Gerrit-Owner: Ben McMillen <ben(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ben McMillen <ben(a)starlabs.systems> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 15 Nov 2022 21:42:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/agah: Add Power Limits for RPL SKU
by Nick Vaccaro (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Tarun Tuli, Tony Huang, Wisley Chen. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69419 ) Change subject: mb/google/brya/var/agah: Add Power Limits for RPL SKU ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f Gerrit-Change-Number: 69419 Gerrit-PatchSet: 3 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 15 Nov 2022 21:18:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/emulation/qemu-q35: Use ioapic helper functions
by Kyösti Mälkki (Code Review) 15 Nov '22

15 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69525 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/emulation/qemu-q35: Use ioapic helper functions ...................................................................... mb/emulation/qemu-q35: Use ioapic helper functions Change-Id: I1b7f4935b6901525b2f3b2a8405c5678aaee7515 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69525 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/emulation/qemu-i440fx/acpi_tables.c 1 file changed, 15 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index 1f10837..61771c7 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -14,8 +14,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) -- To view, visit https://review.coreboot.org/c/coreboot/+/69525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b7f4935b6901525b2f3b2a8405c5678aaee7515 Gerrit-Change-Number: 69525 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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