coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Enable and initialize EINT
by build bot (Jenkins) (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69688 ) Change subject: soc/mediatek/mt8188: Enable and initialize EINT ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163768): https://review.coreboot.org/c/coreboot/+/69688/comment/f8be95d0_85d7a0b2 PS1, Line 12: Root cause and solution: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b Gerrit-Change-Number: 69688 Gerrit-PatchSet: 1 Gerrit-Owner: johnson wang <johnson.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Wed, 16 Nov 2022 10:46:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Enable and initialize EINT
by johnson wang (Code Review) 16 Nov '22

16 Nov '22

johnson wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69688 ) Change subject: soc/mediatek/mt8188: Enable and initialize EINT ...................................................................... soc/mediatek/mt8188: Enable and initialize EINT Issue: Device can't wake up using power button. Root cause and solution: EINT event mask register is used to mask EINT wakeup source. All wakeup sources are masked by default. So we add a driver here to unmask all wakeup sources. BUG=none TEST=device wakes up using power button on MT8188 EVB. Signed-off-by: Johnson Wang <johnson.wang(a)mediatek.com> Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b --- M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/bootblock.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69688/1 diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 13fea31..59ec553 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -10,6 +10,7 @@ all-y += ../common/uart.c bootblock-y += bootblock.c +bootblock-y += ../common/eint_event.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8188/bootblock.c b/src/soc/mediatek/mt8188/bootblock.c index 75fab9a..32ef4af 100644 --- a/src/soc/mediatek/mt8188/bootblock.c +++ b/src/soc/mediatek/mt8188/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <bootblock_common.h> +#include <soc/eint_event.h> #include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/tracker_common.h> @@ -12,4 +13,5 @@ bustracker_init(); mtk_wdt_init(); mt_pll_init(); + unmask_eint_event_mask(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b Gerrit-Change-Number: 69688 Gerrit-PatchSet: 1 Gerrit-Owner: johnson wang <johnson.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/aspeed/common/ast_tables.h: Update to linux master
by Elyes Haouas (Code Review) 16 Nov '22

16 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69676 ) Change subject: drivers/aspeed/common/ast_tables.h: Update to linux master ...................................................................... drivers/aspeed/common/ast_tables.h: Update to linux master Update to master branch at SHA 71dee0361bd04f31c37525e69817654c6e23c97a Change-Id: I89b24a87d4542b6035649f995c14888309a395fa Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/aspeed/common/ast_tables.h 1 file changed, 24 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/69676/1 diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index bfd8f52..7dc6954 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -77,7 +77,7 @@ {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ - {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */ + {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ @@ -119,7 +119,7 @@ {0x44, 0x20, 0x43}, /* 1A: VCLK118_25 */ }; -static struct ast_vbios_stdtable vbios_stdtable[] = { +static const struct ast_vbios_stdtable vbios_stdtable[] = { /* MD_2_3_400 */ { 0x67, @@ -251,6 +251,13 @@ (SyncPP | Charx8Dot), 0xFF, 1, 0x33 }, }; +static const struct ast_vbios_enhtable res_1152x864[] = { + {1600, 1152, 64, 128, 900, 864, 1, 3, VCLK108, /* 75Hz */ + (SyncPP | Charx8Dot | NewModeInfo), 75, 1, 0x3B }, + {1600, 1152, 64, 128, 900, 864, 1, 3, VCLK108, /* end */ + (SyncPP | Charx8Dot | NewModeInfo), 0xFF, 1, 0x3B }, +}; + /* 16:9 */ static const struct ast_vbios_enhtable res_1360x768[] = { {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ @@ -272,10 +279,10 @@ static const struct ast_vbios_enhtable res_1920x1080[] = { {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 1, 0x38 }, {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 0xFF, 1, 0x38 }, }; @@ -319,4 +326,5 @@ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 0xFF, 1, 0x34 }, }; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89b24a87d4542b6035649f995c14888309a395fa Gerrit-Change-Number: 69676 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Subrata Banik (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69680/comment/2acf6bea_eb3d38ea PS1, Line 9: This patch skips setting D0I3 bit for all HECI devices by FSP. > I don't have access to crosbug:200644229. The bug belongs to the brya hotlist. > You can add other information if it makes sense. I'm also curious to know how this CL fix the reported issue. I have updated the commit msg to, kindly read the commit msg and let me know if you still have some questions. -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 10:37:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Subrata Banik (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Subrata Banik has uploaded a new patch set (#2) to the change originally created by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices This patch skips setting D0I3 bit for all HECI devices by FSP. The learning being made from Alder Lake platform showed that the CSE EOP cmd response time is highly nondeterministic and letting the EOP cmd issued by FSP makes the response time even worse. The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute (late sending of EOP) to ensure there is ample time for CSE to come to a state where the response to the EOP is almost immediate. There were a number of refactoring being done to ensure the EOP cmd can be sent at the later stage. #1: Ensure FSP is not putting those HECI devices into the D0i3. (SoC specific change) #2: Modify the CSE related boot state based operation to allow a proper window for sending late EOP cmd. (Common Code Specific change) The entire refactoring helps us to save ~60ms of boot time. Without those code change EOP sending timestamp as below: 943:after sending EOP to ME 1,248,328(61,954)) With those code change EOP sending timestamp as below: 943:after sending EOP to ME 1,231,660 (2,754) Port of commit d6da4ef69e4e ("soc/intel/alderlake: Skip setting D0I3 bit for HECI devices") to incorporate the #1 which is a SoC specific code change. BUG=none TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is set to `1`. Excerpt from google/rex coreboot log: [SPEW ] DisableD0I3SettingForHeci : 0x1 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/69680/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: storage/nvme: Fix different size operands in bitwise operations
by Shahina Shaik (Code Review) 16 Nov '22

16 Nov '22

Shahina Shaik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/69687 ) Change subject: storage/nvme: Fix different size operands in bitwise operations ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/69687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aaa74adee8f909914b848f75525cdcaac0c430a Gerrit-Change-Number: 69687 Gerrit-PatchSet: 1 Gerrit-Owner: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: storage/nvme: Fix different size operands in bitwise operations
by Shahina Shaik (Code Review) 16 Nov '22

16 Nov '22

Shahina Shaik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69687 ) Change subject: storage/nvme: Fix different size operands in bitwise operations ...................................................................... storage/nvme: Fix different size operands in bitwise operations NVME_ADMIN_CRIOCQ_QID and NVME_ADMIN_CRIOCQ_QSIZE macros are used for the cdw10 field, which is of type uint32_t. As a result, the following code sq->cdw10 |= NVME_ADMIN_CRIOCQ_QID(qid); for uint16_t qid leads to an error in Klocwork static analysis. Fix the type returned by these macros (as well as NVME_ADMIN_CRIOCQ_*). BRANCH=none BUG=none TEST=Boot to OS on Nivviks Change-Id: I9aaa74adee8f909914b848f75525cdcaac0c430a Signed-off-by: Shaik Shahina <shahina.shaik(a)intel.com> --- M payloads/external/depthcharge/Makefile 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/69687/1 diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index 687e9f0..d6c0135 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -57,7 +57,9 @@ cd $(project_dir); \ git checkout main; \ git branch -D coreboot 2>/dev/null; \ - git checkout -b coreboot $(TAG-y) + git checkout -b coreboot $(TAG-y); \ + git fetch https://chromium.googlesource.com/chromiumos/platform/depthcharge refs/changes/06/4005406/6; \ + git cherry-pick FETCH_HEAD; ifneq ($(DEPTHCHARGE_MASTER),y) touch $(project_dir)/.version_$(TAG-y) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aaa74adee8f909914b848f75525cdcaac0c430a Gerrit-Change-Number: 69687 Gerrit-PatchSet: 1 Gerrit-Owner: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: transition full control over PM Timer from FSP ...
by Subrata Banik (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69613 ) Change subject: soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: can you please rebase this CL on top of https://review.coreboot.org/c/coreboot/+/69685 to avoid the power penalty? File src/soc/intel/meteorlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/69613/comment/b1c314b4_80d1c83d PS1, Line 362: s_cfg->EnableTcoTimer = 1; NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. -- To view, visit https://review.coreboot.org/c/coreboot/+/69613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027 Gerrit-Change-Number: 69613 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 10:17:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/ironlake,sandybridge/gma: Fix out() parameter order
by Nico Huber (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Angel Pons, Kyösti Mälkki. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69670 ) Change subject: nb/intel/ironlake,sandybridge/gma: Fix out() parameter order ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Patchset: PS1: > Maybe we should drop the code instead? Good question, I assume this is about the OS gfx driver calling us. But I don't think we have anything implemented to handle that. Patchset: PS2: Note, haswell/gma has a similar issue even going down into enable_tco_sci()... -- To view, visit https://review.coreboot.org/c/coreboot/+/69670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4baa2e06d336736caf5505a05ed4353bcbfdb517 Gerrit-Change-Number: 69670 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 10:15:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Sridhar Siricilla (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69680/comment/2a90acff_a6e11a42 PS1, Line 9: This patch skips setting D0I3 bit for all HECI devices by FSP. > > >it's a backport ? […] I don't have access to crosbug:200644229. You can add other information if it makes sense. I'm also curious to know how this CL fix the reported issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 10:12:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2022