coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: mb/google/nissa/var/craask: Disable SAR Proximity Sensor GPIO pin
by Reka Norman (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Tarun Tuli, Kangheui Won, Tyler Wang, Nick Vaccaro, Eric Lai. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69790 ) Change subject: mb/google/nissa/var/craask: Disable SAR Proximity Sensor GPIO pin ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/brya/variants/craask/fw_config.c: File src/mainboard/google/brya/variants/craask/gpio.c: https://review.coreboot.org/c/coreboot/+/69790/comment/518b0383_db99c3d8 PS3, Line 21: PAD_NC(GPP_H19, NONE), This is the same as the baseboard so you can just remove it. -- To view, visit https://review.coreboot.org/c/coreboot/+/69790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2a2516890b68036e96d1a542e6a10a098cb6a7 Gerrit-Change-Number: 69790 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-CC: Victor Ding <victording(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sun, 20 Nov 2022 23:05:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard: Add SPDX license headers to Makefiles
by Michael Niewöhner (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Felix Singer, Jason Nien, Jeremy Soller, Martin Roth, Tim Crawford, Nico Huber, Tarun Tuli, Martin L Roth, Damien Zammit, Subrata Banik, Maxim Polyakov, Kapil Porwal, Alexander Couzens, Werner Zeh, Evgeny Zinoviev. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68982 ) Change subject: mainboard: Add SPDX license headers to Makefiles ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > It's not that AMD is actually demanding this, but the tool that they're using (palamida scan) is, in […] >> As far as the license used, the license of coreboot as a whole is GPL V2. If someone contributes a file and doesn't specify a different license, the license defaults to GPL V2 as a part of the coreboot project. These patches just clarify that the Makefile are licensed under GPL V2. > Is this documented somewhere? As the top-level Makefile is BSD licensed, I would have guessed otherwise. Somehow, yes: https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure License Issues Contributed code must be GPL'd (preferrably 'GPLv2', but 'GPLv2 or any later version' is fine, too). At the very minimum the code must have a GPLv2-compatible license. ^ When there is no license specified I would assume a commit is covered by the "default" license (GPLv2 from COPYING), as Martin said. -- To view, visit https://review.coreboot.org/c/coreboot/+/68982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Gerrit-Change-Number: 68982 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Sun, 20 Nov 2022 22:39:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbflashrom: Add new payload CBFlashrom
by Iman Bingi (Code Review) 20 Nov '22

20 Nov '22

Attention is currently required from: Iman Bingi. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69328 to look at the new patch set (#11). Change subject: payloads/cbflashrom: Add new payload CBFlashrom ...................................................................... payloads/cbflashrom: Add new payload CBFlashrom Flashrom with Graphical User Interface. Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Support for FAT32 file system (USB drives) * Works as ELF payload * Works as Seabios secondary payload * Runs in qemu and on real hardware Shortcomings: * Doesn't work in VGA text mode * Untested TODO: * Test on as many hardware/platforms as possible Change-Id: Ib523ae9eb002f14749942137e53add4986098314 Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig A payloads/cbflashrom/.gitignore A payloads/cbflashrom/Kconfig A payloads/cbflashrom/Makefile A payloads/cbflashrom/NuklearUI/NuklearCBFlashrom.c A payloads/cbflashrom/NuklearUI/NuklearCBFlashrom.h A payloads/cbflashrom/NuklearUI/NuklearCheckbox.c A payloads/cbflashrom/NuklearUI/NuklearCheckbox.h A payloads/cbflashrom/NuklearUI/NuklearCommon.h A payloads/cbflashrom/NuklearUI/NuklearDataGrid.c A payloads/cbflashrom/NuklearUI/NuklearDataGrid.h A payloads/cbflashrom/NuklearUI/NuklearFieldFile.c A payloads/cbflashrom/NuklearUI/NuklearFieldFile.h A payloads/cbflashrom/NuklearUI/NuklearFieldHex.c A payloads/cbflashrom/NuklearUI/NuklearFieldHex.h A payloads/cbflashrom/NuklearUI/NuklearFileChooser.c A payloads/cbflashrom/NuklearUI/NuklearFileChooser.h A payloads/cbflashrom/NuklearUI/NuklearHex.c A payloads/cbflashrom/NuklearUI/NuklearHex.h A payloads/cbflashrom/NuklearUI/NuklearInput.c A payloads/cbflashrom/NuklearUI/NuklearInput.h A payloads/cbflashrom/NuklearUI/NuklearObject.c A payloads/cbflashrom/NuklearUI/NuklearObject.h A payloads/cbflashrom/NuklearUI/NuklearStyle.c A payloads/cbflashrom/NuklearUI/NuklearStyle.h A payloads/cbflashrom/NuklearUI/NuklearUI.h A payloads/cbflashrom/arch/x86/cpuid.c A payloads/cbflashrom/arch/x86/cpuid.h A payloads/cbflashrom/arch/x86/memcpy.c A payloads/cbflashrom/arch/x86/memcpy.h A payloads/cbflashrom/cbflashrom.c A payloads/cbflashrom/cbflashrom.h A payloads/cbflashrom/flashrom/82802ab.c A payloads/cbflashrom/flashrom/COPYING A payloads/cbflashrom/flashrom/Doxyfile A payloads/cbflashrom/flashrom/MAINTAINERS A payloads/cbflashrom/flashrom/Makefile A payloads/cbflashrom/flashrom/Makefile.include A payloads/cbflashrom/flashrom/README A payloads/cbflashrom/flashrom/amd_imc.c A payloads/cbflashrom/flashrom/at45db.c A payloads/cbflashrom/flashrom/atahpt.c A payloads/cbflashrom/flashrom/atavia.c A payloads/cbflashrom/flashrom/bitbang_spi.c A payloads/cbflashrom/flashrom/board_enable.c A payloads/cbflashrom/flashrom/buspirate_spi.c A payloads/cbflashrom/flashrom/cbtable.c A payloads/cbflashrom/flashrom/ch341a_spi.c A payloads/cbflashrom/flashrom/chipset_enable.c A payloads/cbflashrom/flashrom/cli_common.c A payloads/cbflashrom/flashrom/cli_output.c A payloads/cbflashrom/flashrom/custom_baud.c A payloads/cbflashrom/flashrom/dediprog.c A payloads/cbflashrom/flashrom/developerbox_spi.c A payloads/cbflashrom/flashrom/digilent_spi.c A payloads/cbflashrom/flashrom/dirtyjtag_spi.c A payloads/cbflashrom/flashrom/dmi.c A payloads/cbflashrom/flashrom/drkaiser.c A payloads/cbflashrom/flashrom/edi.c A payloads/cbflashrom/flashrom/en29lv640b.c A payloads/cbflashrom/flashrom/flashchips.c A payloads/cbflashrom/flashrom/flashrom.8.tmpl A payloads/cbflashrom/flashrom/flashrom.c A payloads/cbflashrom/flashrom/fmap.c A payloads/cbflashrom/flashrom/ft2232_spi.c A payloads/cbflashrom/flashrom/gfxnvidia.c A payloads/cbflashrom/flashrom/helpers.c A payloads/cbflashrom/flashrom/helpers_fileio.c A payloads/cbflashrom/flashrom/hwaccess_physmap.c A payloads/cbflashrom/flashrom/hwaccess_x86_io.c A payloads/cbflashrom/flashrom/hwaccess_x86_msr.c A payloads/cbflashrom/flashrom/ich_descriptors.c A payloads/cbflashrom/flashrom/ichspi.c A payloads/cbflashrom/flashrom/include/chipdrivers.h A payloads/cbflashrom/flashrom/include/coreboot_tables.h A payloads/cbflashrom/flashrom/include/custom_baud.h A payloads/cbflashrom/flashrom/include/edi.h A payloads/cbflashrom/flashrom/include/ene.h A payloads/cbflashrom/flashrom/include/flash.h A payloads/cbflashrom/flashrom/include/flashchips.h A payloads/cbflashrom/flashrom/include/fmap.h A payloads/cbflashrom/flashrom/include/hwaccess_physmap.h A payloads/cbflashrom/flashrom/include/hwaccess_x86_io.h A payloads/cbflashrom/flashrom/include/hwaccess_x86_msr.h A payloads/cbflashrom/flashrom/include/i2c_helper.h A payloads/cbflashrom/flashrom/include/ich_descriptors.h A payloads/cbflashrom/flashrom/include/layout.h A payloads/cbflashrom/flashrom/include/libflashrom.h A payloads/cbflashrom/flashrom/include/platform.h A payloads/cbflashrom/flashrom/include/platform/pci.h A payloads/cbflashrom/flashrom/include/platform/swap.h A payloads/cbflashrom/flashrom/include/programmer.h A payloads/cbflashrom/flashrom/include/spi.h A payloads/cbflashrom/flashrom/include/usb_device.h A payloads/cbflashrom/flashrom/include/writeprotect.h A payloads/cbflashrom/flashrom/internal.c A payloads/cbflashrom/flashrom/internal.h A payloads/cbflashrom/flashrom/it8212.c A payloads/cbflashrom/flashrom/it87spi.c A payloads/cbflashrom/flashrom/jedec.c A payloads/cbflashrom/flashrom/jlink_spi.c A payloads/cbflashrom/flashrom/known_boards.c A payloads/cbflashrom/flashrom/layout.c A payloads/cbflashrom/flashrom/libflashrom.c A payloads/cbflashrom/flashrom/libflashrom.map A payloads/cbflashrom/flashrom/mcp6x_spi.c A payloads/cbflashrom/flashrom/meson.build A payloads/cbflashrom/flashrom/meson_options.txt A payloads/cbflashrom/flashrom/mstarddc_spi.c A payloads/cbflashrom/flashrom/nic3com.c A payloads/cbflashrom/flashrom/nicintel.c A payloads/cbflashrom/flashrom/nicintel_eeprom.c A payloads/cbflashrom/flashrom/nicintel_spi.c A payloads/cbflashrom/flashrom/nicnatsemi.c A payloads/cbflashrom/flashrom/nicrealtek.c A payloads/cbflashrom/flashrom/ogp_spi.c A payloads/cbflashrom/flashrom/opaque.c A payloads/cbflashrom/flashrom/parade_lspcon.c A payloads/cbflashrom/flashrom/parallel.c A payloads/cbflashrom/flashrom/pcidev.c A payloads/cbflashrom/flashrom/pickit2_spi.c A payloads/cbflashrom/flashrom/platform/endian_big.c A payloads/cbflashrom/flashrom/platform/endian_little.c A payloads/cbflashrom/flashrom/platform/memaccess.c A payloads/cbflashrom/flashrom/platform/meson.build A payloads/cbflashrom/flashrom/pony_spi.c A payloads/cbflashrom/flashrom/processor_enable.c A payloads/cbflashrom/flashrom/programmer.c A payloads/cbflashrom/flashrom/programmer_table.c A payloads/cbflashrom/flashrom/raiden_debug_spi.c A payloads/cbflashrom/flashrom/rayer_spi.c A payloads/cbflashrom/flashrom/realtek_mst_i2c_spi.c A payloads/cbflashrom/flashrom/s25f.c A payloads/cbflashrom/flashrom/satamv.c A payloads/cbflashrom/flashrom/satasii.c A payloads/cbflashrom/flashrom/sb600spi.c A payloads/cbflashrom/flashrom/serprog.c A payloads/cbflashrom/flashrom/sfdp.c A payloads/cbflashrom/flashrom/spi.c A payloads/cbflashrom/flashrom/spi25.c A payloads/cbflashrom/flashrom/spi25_statusreg.c A payloads/cbflashrom/flashrom/spi95.c A payloads/cbflashrom/flashrom/sst28sf040.c A payloads/cbflashrom/flashrom/sst49lfxxxc.c A payloads/cbflashrom/flashrom/sst_fwhub.c A payloads/cbflashrom/flashrom/stlinkv3_spi.c A payloads/cbflashrom/flashrom/stm50.c A payloads/cbflashrom/flashrom/test_build.sh A payloads/cbflashrom/flashrom/udelay.c A payloads/cbflashrom/flashrom/usb_device.c A payloads/cbflashrom/flashrom/usbblaster_spi.c A payloads/cbflashrom/flashrom/usbdev.c A payloads/cbflashrom/flashrom/w29ee011.c A payloads/cbflashrom/flashrom/w39.c A payloads/cbflashrom/flashrom/wbsio_spi.c A payloads/cbflashrom/flashrom/writeprotect.c A payloads/cbflashrom/flashrom/writeprotect_ranges.c A payloads/cbflashrom/fsys/usbstorage.c A payloads/cbflashrom/fsys/usbstorage.h A payloads/cbflashrom/gfx/gfx.c A payloads/cbflashrom/gfx/gfx.h A payloads/cbflashrom/gfx/splash.c A payloads/cbflashrom/gfx/splash.h A payloads/cbflashrom/lang/en.c A payloads/cbflashrom/lang/lang.c A payloads/cbflashrom/lang/lang.h A payloads/cbflashrom/libftdi/LICENSE A payloads/cbflashrom/libftdi/src/ftdi.c A payloads/cbflashrom/libftdi/src/ftdi.h A payloads/cbflashrom/libftdi/src/ftdi_i.h A payloads/cbflashrom/libftdi/src/ftdi_stream.c A payloads/cbflashrom/libjaylink/buffer.c A payloads/cbflashrom/libjaylink/core.c A payloads/cbflashrom/libjaylink/device.c A payloads/cbflashrom/libjaylink/discovery.c A payloads/cbflashrom/libjaylink/discovery_usb.c A payloads/cbflashrom/libjaylink/emucom.c A payloads/cbflashrom/libjaylink/error.c A payloads/cbflashrom/libjaylink/fileio.c A payloads/cbflashrom/libjaylink/jtag.c A payloads/cbflashrom/libjaylink/libjaylink-internal.h A payloads/cbflashrom/libjaylink/libjaylink.h A payloads/cbflashrom/libjaylink/list.c A payloads/cbflashrom/libjaylink/log.c A payloads/cbflashrom/libjaylink/strutil.c A payloads/cbflashrom/libjaylink/swd.c A payloads/cbflashrom/libjaylink/swo.c A payloads/cbflashrom/libjaylink/target.c A payloads/cbflashrom/libjaylink/transport.c A payloads/cbflashrom/libjaylink/transport_usb.c A payloads/cbflashrom/libjaylink/util.c A payloads/cbflashrom/libusb/libusb.c A payloads/cbflashrom/libusb/libusb.h A payloads/cbflashrom/logo/cbui.png A payloads/cbflashrom/lp.config A payloads/cbflashrom/util/buffers.c A payloads/cbflashrom/util/buffers.h A payloads/cbflashrom/util/vector.c A payloads/cbflashrom/util/vector.h 199 files changed, 91,910 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/69328/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/69328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib523ae9eb002f14749942137e53add4986098314 Gerrit-Change-Number: 69328 Gerrit-PatchSet: 11 Gerrit-Owner: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/kconfig: Re-add KCONFIG_SPLITCONFIG functionality
by Nicholas Chin (Code Review) 20 Nov '22

20 Nov '22

Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69450 ) Change subject: util/kconfig: Re-add KCONFIG_SPLITCONFIG functionality ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Hey, I'm sorry, I didn't see this and pushed my own patch - it's pretty much identical to yours. […] Oh well, it happens. In that case I'll abandon this patch. I also just pushed a patch to fix the diff formatting of your patch, as it is incompatible with the quilt tool. CB:69863 -- To view, visit https://review.coreboot.org/c/coreboot/+/69450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dd36edb0c36d7679896fde6f84e8471589d83a1 Gerrit-Change-Number: 69450 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 20 Nov 2022 18:11:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/kconfig: Re-add KCONFIG_SPLITCONFIG functionality
by Nicholas Chin (Code Review) 20 Nov '22

20 Nov '22

Nicholas Chin has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/69450 ) Change subject: util/kconfig: Re-add KCONFIG_SPLITCONFIG functionality ...................................................................... Abandoned CB:69535 was merged first -- To view, visit https://review.coreboot.org/c/coreboot/+/69450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dd36edb0c36d7679896fde6f84e8471589d83a1 Gerrit-Change-Number: 69450 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: util/kconfig: Fix patch to be compatible with quilt
by build bot (Jenkins) (Code Review) 20 Nov '22

20 Nov '22

Attention is currently required from: Martin L Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69863 ) Change subject: util/kconfig: Fix patch to be compatible with quilt ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164098): https://review.coreboot.org/c/coreboot/+/69863/comment/da105619_0d21cad4 PS1, Line 8: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit b7f92a0b6a0f ("util/kconfig: Add patch to move Kconfig deps to build/config")' -- To view, visit https://review.coreboot.org/c/coreboot/+/69863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95bfe6571e3a2cc2b38074b4338f1610a4c8a595 Gerrit-Change-Number: 69863 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sun, 20 Nov 2022 18:06:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/kconfig: Fix patch to be compatible with quilt
by Nicholas Chin (Code Review) 20 Nov '22

20 Nov '22

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69863 ) Change subject: util/kconfig: Fix patch to be compatible with quilt ...................................................................... util/kconfig: Fix patch to be compatible with quilt The patch added in commit b7f92a0b6a0f (util/kconfig: Add patch to move Kconfig deps to build/config) uses git diff formatting, which is incompatible with quilt. Change-Id: I95bfe6571e3a2cc2b38074b4338f1610a4c8a595 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch 1 file changed, 20 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/69863/1 diff --git a/util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch b/util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch index fb85035..b4db86e 100644 --- a/util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch +++ b/util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch @@ -17,11 +17,11 @@ util/kconfig/confdata.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) -diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c -index 95fb960179..3da9e8b38d 100644 ---- a/util/kconfig/confdata.c -+++ b/util/kconfig/confdata.c -@@ -230,6 +230,13 @@ static const char *conf_get_autoheader_name(void) +Index: kconfig/confdata.c +=================================================================== +--- kconfig.orig/confdata.c ++++ kconfig/confdata.c +@@ -230,6 +230,13 @@ static const char *conf_get_autoheader_n return name ? name : "include/generated/autoconf.h"; } @@ -35,7 +35,7 @@ static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p) { char *p2; -@@ -1024,19 +1031,14 @@ static int conf_write_autoconf_cmd(const char *autoconf_name) +@@ -1024,19 +1031,14 @@ static int conf_write_autoconf_cmd(const static int conf_touch_deps(void) { @@ -59,6 +59,3 @@ conf_read_simple(name, S_DEF_AUTO); sym_calc_value(modules_sym); --- -2.30.2 - -- To view, visit https://review.coreboot.org/c/coreboot/+/69863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95bfe6571e3a2cc2b38074b4338f1610a4c8a595 Gerrit-Change-Number: 69863 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mainboard/msi/ms7d25: Configure NCT6687D pin for PECI
by Martin L Roth (Code Review) 20 Nov '22

20 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68711 ) Change subject: mainboard/msi/ms7d25: Configure NCT6687D pin for PECI ...................................................................... mainboard/msi/ms7d25: Configure NCT6687D pin for PECI One register configuring multi-pin functions was outside of the Global Configuration Registers space and skipped in the initial port patches. Replicate the vendor configuration and set the Super I/O pin for PECI functionality. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/msi/ms7d25/bootblock.c 1 file changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/msi/ms7d25/bootblock.c b/src/mainboard/msi/ms7d25/bootblock.c index 2dcb763..110d682 100644 --- a/src/mainboard/msi/ms7d25/bootblock.c +++ b/src/mainboard/msi/ms7d25/bootblock.c @@ -6,6 +6,7 @@ #include <superio/nuvoton/nct6687d/nct6687d.h> #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) +#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) void bootblock_mainboard_early_init(void) { @@ -13,6 +14,8 @@ nuvoton_pnp_enter_conf_state(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + + /* Below are multi-pin function */ pnp_write_config(SERIAL_DEV, 0x15, 0xaa); pnp_write_config(SERIAL_DEV, 0x1a, 0x02); pnp_write_config(SERIAL_DEV, 0x1b, 0x02); @@ -31,7 +34,12 @@ pnp_write_config(SERIAL_DEV, 0x2b, 0x20); pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); - nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + pnp_set_logical_device(POWER_DEV); + /* Configure pin for PECI */ + pnp_write_config(POWER_DEV, 0xf3, 0x80); + + nuvoton_pnp_exit_conf_state(POWER_DEV); if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -- To view, visit https://review.coreboot.org/c/coreboot/+/68711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b Gerrit-Change-Number: 68711 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: device/pciexp: add pcie_find_dsn()
by Martin L Roth (Code Review) 20 Nov '22

20 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54510 ) Change subject: device/pciexp: add pcie_find_dsn() ...................................................................... device/pciexp: add pcie_find_dsn() Add pcie_find_dsn() to detect and match PCIe device serial number. In addition, vendor ID is matched when provided. Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54510 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> --- M src/device/pciexp_device.c M src/include/device/pciexp.h 2 files changed, 70 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index b03089b..c9441fb 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -93,6 +93,57 @@ } } +/** + * Find a PCIe device with a given serial number, and a given VID if applicable + * + * @param serial The serial number of the device. + * @param vid Vendor ID of the device, may be 0 if not applicable. + * @param from Pointer to the device structure, used as a starting point in + * the linked list of all_devices, which can be 0 to start at the + * head of the list (i.e. all_devices). + * @return Pointer to the device struct. + */ +struct device *pcie_find_dsn(const uint64_t serial, const uint16_t vid, + struct device *from) +{ + union dsn { + struct { + uint32_t dsn_low; + uint32_t dsn_high; + }; + uint64_t dsn; + } dsn; + unsigned int cap; + uint16_t vendor_id; + + if (!from) + from = all_devices; + else + from = from->next; + + while (from) { + if (from->path.type == DEVICE_PATH_PCI) { + cap = pciexp_find_extended_cap(from, PCI_EXT_CAP_ID_DSN, 0); + /* + * For PCIe device, find extended capability for serial number. + * The capability header is 4 bytes, followed by lower 4 bytes + * of serial number, then higher 4 byes of serial number. + */ + if (cap != 0) { + dsn.dsn_low = pci_read_config32(from, cap + 4); + dsn.dsn_high = pci_read_config32(from, cap + 8); + vendor_id = pci_read_config16(from, PCI_VENDOR_ID); + if ((dsn.dsn == serial) && (vid == 0 || vendor_id == vid)) + return from; + } + } + + from = from->next; + } + + return from; +} + /* * Re-train a PCIe link */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index d816240..9f9c28e 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -44,6 +44,9 @@ type == PCI_EXP_TYPE_PCIE_BRIDGE; } +struct device *pcie_find_dsn(const uint64_t serial, const uint16_t vid, + struct device *from); + bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop); #endif /* DEVICE_PCIEXP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618b Gerrit-Change-Number: 54510 Gerrit-PatchSet: 15 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: acpi: Add initial support for CEDT
by Martin L Roth (Code Review) 20 Nov '22

20 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64263 ) Change subject: acpi: Add initial support for CEDT ...................................................................... acpi: Add initial support for CEDT Add initial CEDT (CXL Early Discovery Table) support based on CXL spec 2.0 section 9.14.1. Add functions to create CEDT table (revision 1), and create CEDT CXL Host Bridge Structure (CHBS) and CXL Fixed Memory Windows Structure (CFMWS). TESTED=Create CEDT table on Intel Archer City CRB, dumped the CEDT table and examined the content. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64263 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 173 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e1d4088..8d81284 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -575,6 +575,90 @@ header->checksum = acpi_checksum((void *)srat, header->length); } +int acpi_create_cedt_chbs(acpi_cedt_chbs_t *chbs, u32 uid, u32 cxl_ver, u64 base) +{ + memset((void *)chbs, 0, sizeof(acpi_cedt_chbs_t)); + + chbs->type = ACPI_CEDT_STRUCTURE_CHBS; + chbs->length = sizeof(acpi_cedt_chbs_t); + chbs->uid = uid; + chbs->cxl_ver = cxl_ver; + chbs->base = base; + + /* + * CXL spec 2.0 section 9.14.1.2 "CXL CHBS" + * CXL 1.1 spec compliant host bridge: 8KB + * CXL 2.0 spec compliant host bridge: 64KB + */ + if (cxl_ver == ACPI_CEDT_CHBS_CXL_VER_1_1) + chbs->len = 8 * KiB; + else if (cxl_ver == ACPI_CEDT_CHBS_CXL_VER_2_0) + chbs->len = 64 * KiB; + else + printk(BIOS_ERR, "ACPI(%s:%s): Incorrect CXL version:%d\n", __FILE__, __func__, + cxl_ver); + + return chbs->length; +} + +int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_size, u8 eniw, + u32 hbig, u16 restriction, u16 qtg_id, const u32 *interleave_target) +{ + memset((void *)cfmws, 0, sizeof(acpi_cedt_cfmws_t)); + + cfmws->type = ACPI_CEDT_STRUCTURE_CFMWS; + + u8 niw = 0; + if (eniw >= 8) + printk(BIOS_ERR, "ACPI(%s:%s): Incorrect eniw::%d\n", __FILE__, __func__, eniw); + else + /* NIW = 2 ** ENIW */ + niw = 0x1 << eniw; + /* 36 + 4 * NIW */ + cfmws->length = sizeof(acpi_cedt_cfmws_t) + 4 * niw; + + cfmws->base_hpa = base_hpa; + cfmws->window_size = window_size; + cfmws->eniw = eniw; + + // 0: Standard Modulo Arithmetic. Other values reserved. + cfmws->interleave_arithmetic = 0; + + cfmws->hbig = hbig; + cfmws->restriction = restriction; + cfmws->qtg_id = qtg_id; + memcpy(&cfmws->interleave_target, interleave_target, 4 * niw); + + return cfmws->length; +} + +void acpi_create_cedt(acpi_cedt_t *cedt, unsigned long (*acpi_fill_cedt)(unsigned long current)) +{ + acpi_header_t *header = &(cedt->header); + unsigned long current = (unsigned long)cedt + sizeof(acpi_cedt_t); + + memset((void *)cedt, 0, sizeof(acpi_cedt_t)); + + if (!header) + return; + + /* Fill out header fields. */ + memcpy(header->signature, "CEDT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->asl_compiler_revision = asl_revision; + header->length = sizeof(acpi_cedt_t); + header->revision = get_acpi_table_revision(CEDT); + + current = acpi_fill_cedt(current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)cedt; + header->checksum = acpi_checksum((void *)cedt, header->length); +} + int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory) { memset((void *)mpda, 0, sizeof(acpi_hmat_mpda_t)); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index d7fc243..fa216aa 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -72,8 +72,8 @@ enum acpi_tables { /* Tables defined by ACPI and used by coreboot */ - BERT, DBG2, DMAR, DSDT, EINJ, FACS, FADT, HEST, HMAT, HPET, IVRS, MADT, - MCFG, RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, + BERT, CEDT, DBG2, DMAR, DSDT, EINJ, FACS, FADT, HEST, HMAT, HPET, IVRS, + MADT, MCFG, RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, /* Additional proprietary tables used by coreboot */ VFCT, NHLT, SPMI, CRAT }; @@ -222,6 +222,60 @@ } __packed acpi_mcfg_mmconfig_t; /* + * CEDT (CXL Early Discovery Table) + * CXL spec 2.0 section 9.14.1 + */ +typedef struct acpi_cedt { + acpi_header_t header; + /* Followed by CEDT structures[n] */ +} __packed acpi_cedt_t; + +#define ACPI_CEDT_STRUCTURE_CHBS 0 +#define ACPI_CEDT_STRUCTURE_CFMWS 1 + +#define ACPI_CEDT_CHBS_CXL_VER_1_1 0x00 +#define ACPI_CEDT_CHBS_CXL_VER_2_0 0x01 + +/* CHBS: CXL Host Bridge Structure */ +typedef struct acpi_cedt_chbs { + u8 type; /* Always 0, other values reserved */ + u8 resv1; + u16 length; /* Length in bytes (32) */ + u32 uid; /* CXL Host Bridge Unique ID */ + u32 cxl_ver; + u32 resv2; + /* + * For CXL 1.1, the base is Downstream Port Root Complex Resource Block; + * For CXL 2.0, the base is CXL Host Bridge Component Registers. + */ + u64 base; + u64 len; +} __packed acpi_cedt_chbs_t; + +#define ACPI_CEDT_CFMWS_RESTRICTION_TYPE_2_MEM (1 << 0) +#define ACPI_CEDT_CFMWS_RESTRICTION_TYPE_3_MEM (1 << 1) +#define ACPI_CEDT_CFMWS_RESTRICTION_VOLATIL (1 << 2) +#define ACPI_CEDT_CFMWS_RESTRICTION_PERSISTENT (1 << 3) +#define ACPI_CEDT_CFMWS_RESTRICTION_FIXED (1 << 4) + +/* CFMWS: CXL Fixed Memory Window Structure */ +typedef struct acpi_cedt_cfmws { + u8 type; /* Type (0) */ + u8 resv1; + u16 length; /* Length in bytes (32) */ + u32 resv2; + u64 base_hpa; /* Base of the HPA range, 256MB aligned */ + u64 window_size; /* Number of bytes this window represents */ + u8 eniw; /* Encoded Number of Interleave Ways */ + u8 interleave_arithmetic; /* Standard Modulo arithmetic (0) */ + u16 resv3; + u32 hbig; /* Host Bridge Interleave Granularity */ + u16 restriction; + u16 qtg_id; + u32 interleave_target[]; /* Interleave Target List */ +} __packed acpi_cedt_cfmws_t; + +/* * HMAT (Heterogeneous Memory Attribute Table) * ACPI spec 6.4 section 5.2.27 */ @@ -1260,6 +1314,15 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table); +/* Create CXL Early Discovery Table */ +void acpi_create_cedt(acpi_cedt_t *cedt, + unsigned long (*acpi_fill_cedt)(unsigned long current)); +/* Create a CXL Host Bridge Structure for CEDT */ +int acpi_create_cedt_chbs(acpi_cedt_chbs_t *chbs, u32 uid, u32 cxl_ver, u64 base); +/* Create a CXL Fixed Memory Window Structure for CEDT */ +int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_size, + u8 eniw, u32 hbig, u16 restriction, u16 qtg_id, const u32 *interleave_target); + int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic); int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base); -- To view, visit https://review.coreboot.org/c/coreboot/+/64263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802 Gerrit-Change-Number: 64263 Gerrit-PatchSet: 10 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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