Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal.
Hello Tarun Tuli, Subrata Banik, Kapil Porwal,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69884
to look at the new patch set (#5).
Change subject: vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.h
......................................................................
vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.h
Changes include:
- FirmwareVersionInfoHob.h is removed to use new FirmwareVersionInfo.h
BUG=TBD
BRANCH=None
TEST=Verify MTL Rex0 build with all the patch in relation chain
and verify the version output prints no junk data observed.
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
Change-Id: I06fd89f201e9e4100524e58033086327ad4ffc7b
---
D src/vendorcode/intel/fsp/fsp2_0/meteorlake/FirmwareVersionInfoHob.h
1 file changed, 18 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/69884/5
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Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69396 )
Change subject: mb/intel/mtlrvp: Configure devicetree and GPIOs for Meteor Lake-P
......................................................................
Patch Set 14: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69396/comment/fd077c84_dafe43a5
PS13, Line 9: Add devicetree and GPIO configuration for Metero Lake-P.
> nit: Meteor Lake-P.
Ack
File src/mainboard/intel/mtlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/69396/comment/ea85e737_2a11feb7
PS13, Line 16: select HAVE_ACPI_RESUME
> nit: Alphabetically order the Kconfigs.
Ack
File src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/69396/comment/743adfdd_194fb6d3
PS13, Line 1: chip soc/intel/alderlake
> meteorlake
Ack
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Hello Ashish Kumar Mishra, build bot (Jenkins), Haribalaraman Ramasubramanian, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Krishna P Bhat D, Eric Lai, Usha P,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69396
to look at the new patch set (#14).
Change subject: mb/intel/mtlrvp: Configure devicetree and GPIOs for Meteor Lake-P
......................................................................
mb/intel/mtlrvp: Configure devicetree and GPIOs for Meteor Lake-P
Add devicetree and GPIO configuration for Meteor Lake-P.
Changes include,
1. Modify existing devicetree.cb to support MTL-RVP board and variant
2. Add separate file for MTL-P GPIOs
3. Add overridetree MTL-P variant
BRANCH=none
BUG=b:224325352
TEST=emerge-rex coreboot chromeos-bootimage
Signed-off-by: Harsha B R <harsha.b.r(a)intel.com>
Change-Id: I3173c3f32b36d24467431df3652badd70efeab93
---
M src/mainboard/intel/mtlrvp/Kconfig
M src/mainboard/intel/mtlrvp/Makefile.inc
M src/mainboard/intel/mtlrvp/devicetree.cb
A src/mainboard/intel/mtlrvp/gpio.c
A src/mainboard/intel/mtlrvp/include/baseboard/board_id.h
A src/mainboard/intel/mtlrvp/include/baseboard/variants.h
A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb
7 files changed, 1,113 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/69396/14
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Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
......................................................................
Patch Set 31:
(1 comment)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/a8e850d7_9382d3cb
PS16, Line 393: #else
> My concern is that the new fields added to `DPTC_INPUTS()` need to be added to `google/skyrim/varian […]
for below settings
vrm_current_limit_throttle_mA,
vrm_maximum_current_limit_throttle_mA,
vrm_soc_current_limit_throttle_mA,
since the below settings will apply to dptc parameters, it's better to follow AMD IRM, or you have your own setting that needs to apply to.
There's no other STT setting that will be changed via DPTC, so those values will keep the value you set to default in devtree.
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69160 )
Change subject: security/tpm: resolve conflicts in TSS implementations
......................................................................
Patch Set 8:
(6 comments)
File src/security/tpm/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69160/comment/6b11723c_df60b8d6
PS8, Line 13: ramstage-y += tss/tss.c
: romstage-y += tss/tss.c
: bootblock-y += tss/tss.c
: verstage-y += tss/tss.c
: postcar-y += tss/tss.c
Can use `all-y` for all classes (bootblock verstage romstage postcar ramstage).
File src/security/tpm/tss.h:
https://review.coreboot.org/c/coreboot/+/69160/comment/3e8c476c_4ffd9ff9
PS8, Line 19: #include <security/tpm/tis.h>
Sort the headers.
File src/security/tpm/tss/tss.c:
https://review.coreboot.org/c/coreboot/+/69160/comment/378eba8e_53fecf91
PS8, Line 17: chose
choose
https://review.coreboot.org/c/coreboot/+/69160/comment/7712adac_bbb78d57
PS8, Line 20:
Extra blank line.
https://review.coreboot.org/c/coreboot/+/69160/comment/1b9f60ae_ddee9817
PS8, Line 22: VB2_SUCCESS
Not related to your change, but why does this function return VB2_*? Can't we just return something like 0/1/-1 here?
https://review.coreboot.org/c/coreboot/+/69160/comment/4d2fe69b_39407363
PS8, Line 37: if (CONFIG(TPM1) && family == TPM_1)
: return tlcl1_startup();
: if (CONFIG(TPM2) && family == TPM_2)
: return tlcl2_startup();
: return TPM_E_INTERNAL_INCONSISTENCY;
I wonder if we can define a macro to simplify the functions below:
```
#define TLCL_CALL(name, ...) do {
if (CONFIG(TPM1) && family == TPM_1)
return tlcl1_##name(__VA_ARGS__);
...
} while (0)
```
Then we could use it like
```
TLCL_CALL(extend, pcr_num, in_digest, out_digest);
```
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