coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
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[S] Change in coreboot[master]: mb/google/brya: add missing devices to DSDT
by Eric Lai (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Eran Mitrani, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69392 ) Change subject: mb/google/brya: add missing devices to DSDT ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/brya/dsdt.asl: https://review.coreboot.org/c/coreboot/+/69392/comment/a09d6a54_845cb4dc PS4, Line 32: Device (FSPI) {} > Moved FSPI to a separate CL, and removed DPTF from this CL since it already has an entry in SSDT (bu […] Should this be addressed in the sconfig? _SB.PCI0.DPTF -- To view, visit https://review.coreboot.org/c/coreboot/+/69392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d53913c8da07b093e479ed8e12fda8c9990e3d Gerrit-Change-Number: 69392 Gerrit-PatchSet: 6 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 01:01:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Eran Mitrani <mitrani(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: add missing devices to DSDT
by Eric Lai (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Eran Mitrani, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69392 ) Change subject: mb/google/brya: add missing devices to DSDT ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/brya/dsdt.asl: https://review.coreboot.org/c/coreboot/+/69392/comment/ff95adc5_783b0c55 PS6, Line 29: Device (SRAM) {} It would be good to ask Intel create driver entry for device ref shared_sram on end https://review.coreboot.org/c/coreboot/+/69392/comment/a3b3bd31_8042c426 PS6, Line 30: Device (HEC1) {} It would be good to ask Intel create driver entry for device ref heci1 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/69392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d53913c8da07b093e479ed8e12fda8c9990e3d Gerrit-Change-Number: 69392 Gerrit-PatchSet: 6 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 00:59:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: add missing devices to DSDT
by Eran Mitrani (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Eric Lai. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69392 ) Change subject: mb/google/brya: add missing devices to DSDT ...................................................................... Patch Set 6: (2 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/69392/comment/79a4d722_5ce87727 PS4, Line 10: SHA > commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07 Done File src/mainboard/google/brya/dsdt.asl: https://review.coreboot.org/c/coreboot/+/69392/comment/4f693f9e_156e841d PS4, Line 32: Device (FSPI) {} > Those looks like the Intel device APCI. And should include when enable the device in device tree. […] Moved FSPI to a separate CL, and removed DPTF from this CL since it already has an entry in SSDT (but under _SB.DPTF directly which is not matching the location in the devicetree file _SB.PCI0.DPTF) -- To view, visit https://review.coreboot.org/c/coreboot/+/69392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d53913c8da07b093e479ed8e12fda8c9990e3d Gerrit-Change-Number: 69392 Gerrit-PatchSet: 6 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 00:56:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vboot: Fix hash digest size, padding and comparison
by Julius Werner (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Jakub Czapiga, Caveh Jalali, Yu-Ping Wu, Boris Mittelberg. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69762 ) Change subject: vboot: Fix hash digest size, padding and comparison ...................................................................... Patch Set 5: (1 comment) File src/security/vboot/vboot_logic.c: https://review.coreboot.org/c/coreboot/+/69762/comment/5d4f5d44_ddd87734 PS5, Line 99: if (slot_hash_sz < saved_hash_sz) { Not sure why we need to bother checking the extra zeroes? -- To view, visit https://review.coreboot.org/c/coreboot/+/69762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Gerrit-Change-Number: 69762 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 00:51:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/adl/acpi: add FSPI to DSDT
by Eran Mitrani (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69920 to look at the new patch set (#2). Change subject: soc/intel/adl/acpi: add FSPI to DSDT ...................................................................... soc/intel/adl/acpi: add FSPI to DSDT A previous CL ("Add missing ACPI device path names", SHA d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors from the Kernel on Brya devices (see Tim's comment on patchset 8): > ACPI Error: AE_NOT_FOUND, While resolving a named reference > package element - \_SB_.PCI0.FSPI FSPI is defined in src/soc/intel/alderlake/chipset.cbi: device pci 1f.5 alias fast_spi on end This CL adds the corresponding FSPI device to the DSDT to prevent the error mentioned above. TEST=Built and tested on brya by verifying the error is gone. BUG=b:231582182 Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c --- M src/soc/intel/alderlake/acpi/serialio.asl 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69920/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c Gerrit-Change-Number: 69920 Gerrit-PatchSet: 2 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/adl/acpi:add FSPI to DSDT
by Eran Mitrani (Code Review) 23 Nov '22

23 Nov '22

Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69920 ) Change subject: soc/intel/adl/acpi:add FSPI to DSDT ...................................................................... soc/intel/adl/acpi:add FSPI to DSDT A previous CL ("Add missing ACPI device path names", SHA d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors from the Kernel on Brya devices (see Tim's comment on patchset 8): > ACPI Error: AE_NOT_FOUND, While resolving a named reference > package element - \_SB_.PCI0.FSPI FSPI is defined in src/soc/intel/alderlake/chipset.cbi: device pci 1f.5 alias fast_spi on end This CL adds the corresponding FSPI device to the DSDT to prevent the error mentioned above. TEST=Built and tested on brya by verifying the error is gone. BUG=b:231582182 Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c --- M src/soc/intel/alderlake/acpi/serialio.asl 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69920/1 diff --git a/src/soc/intel/alderlake/acpi/serialio.asl b/src/soc/intel/alderlake/acpi/serialio.asl index 93632fc..3747d9e 100644 --- a/src/soc/intel/alderlake/acpi/serialio.asl +++ b/src/soc/intel/alderlake/acpi/serialio.asl @@ -50,6 +50,12 @@ Name (_DDN, "Serial IO I2C Controller 7") } +Device (FSPI) +{ + Name (_ADR, 0x001f0005) + Name (_DDN, "Fast SPI") +} + Device (SPI0) { Name (_ADR, 0x001e0002) -- To view, visit https://review.coreboot.org/c/coreboot/+/69920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c Gerrit-Change-Number: 69920 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/brya/var/craask: Modify GPIOs for craaskneto/craaskino
by Reka Norman (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, David Wu, Kangheui Won, Ren Kuo, Tyler Wang, Nick Vaccaro, Eric Lai. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69693 ) Change subject: mb/google/brya/var/craask: Modify GPIOs for craaskneto/craaskino ...................................................................... Patch Set 6: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69693/comment/50ba9ce2_6426fa98 PS6, Line 7: brya nit: nissa File src/mainboard/google/brya/variants/craask/fw_config.c: https://review.coreboot.org/c/coreboot/+/69693/comment/f60ca872_f5d46d70 PS6, Line 20: _extern `_extend` to be consistent with gpio.c? https://review.coreboot.org/c/coreboot/+/69693/comment/88d63256_0a9c1d91 PS6, Line 68: if (id < 0x20) { Since the LTE pads are the only ones that differ, can you put the if statement around the LTE block only? See nivviks for an example. https://review.coreboot.org/c/coreboot/+/69693/comment/5ed0af26_45413370 PS6, Line 103: gpio_padbased_override(padbased_table, wfc_disable_pads, > Since you're disabling MIPI WFC in both cases ((id >= 0x20) || (id < 0x20)), why not just set the pa […] For (id < 0x20), they're only disabled if the fw_config is not set, so I think we still need it in fw_config.c. But I don't think we need to handle the (id < 0x20) and (id >= 0x20) cases differently. If the WFC is not present on (id >= 0x20), the fw_config should not be set. So we can move this outside the `if (id < 0x20)` statement, as I suggested above. -- To view, visit https://review.coreboot.org/c/coreboot/+/69693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9c90abe562768ea2afff5608a8cfac764569d5 Gerrit-Change-Number: 69693 Gerrit-PatchSet: 6 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 00:45:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vboot/vboot_common: Fix vboot_save_data() code exclusion guard
by Julius Werner (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Jakub Czapiga. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69761 ) Change subject: vboot/vboot_common: Fix vboot_save_data() code exclusion guard ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69761/comment/060f69eb_18b11b6c PS4, Line 12: reduction of undefined references. I find this hard to believe... this looks like a purely cosmetic change to me that should make no difference to the compiler. Can you explain what exactly you built and where you found evidence of bad code generation? -- To view, visit https://review.coreboot.org/c/coreboot/+/69761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Gerrit-Change-Number: 69761 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 00:44:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by Tim Van Patten (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Eric Peers, Jason Glenesk, Dtrain Hsu, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 59: (2 comments) File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/c06183df_57a7929a PS59, Line 22: /* If _SB.DTTS is not present, DTTS is not enabled. */ : If (CondRefOf (\_SB.DTTS)) : { : \_SB.DTTS() : Return (Zero) : } This needs to be moved down to ref1. https://review.coreboot.org/c/coreboot/+/68471/comment/0434dfae_ad642000 PS59, Line 52: ref1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 59 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Nov 2022 00:41:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: device/xhci: Refactor functions to work with a non-const device tree
by build bot (Jenkins) (Code Review) 23 Nov '22

23 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69914 ) Change subject: device/xhci: Refactor functions to work with a non-const device tree ...................................................................... Patch Set 2: (2 comments) File src/device/xhci_const.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164337): https://review.coreboot.org/c/coreboot/+/69914/comment/84aec2f4_f9a87a13 PS2, Line 18: enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164337): https://review.coreboot.org/c/coreboot/+/69914/comment/a5d5101f_5eb4a2dc PS2, Line 95: enum cb_err xhci_resource_for_each_supported_usb_cap( that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/69914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Gerrit-Change-Number: 69914 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Nov 2022 23:09:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2022