coreboot-gerrit November 2022

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[M] Change in coreboot[master]: mb/google/brya/var/craask: Modify GPIOs for craaskneto/craaskino
by Ren Kuo (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, David Wu, Kangheui Won, Ren Kuo, Tyler Wang, Nick Vaccaro, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, David Wu, Kangheui Won, Reka Norman, Tyler Wang, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69693 to look at the new patch set (#7). Change subject: mb/google/brya/var/craask: Modify GPIOs for craaskneto/craaskino ...................................................................... mb/google/brya/var/craask: Modify GPIOs for craaskneto/craaskino Modify GPIOs for craaskneto/craaskino: 1. Define the extend table for bootblock, romstage, and ramstage. Disable the unused WFC and LTE in gpio table. 2. Modfiy fw_config gpio table to skip the LTE and WFC from craask. 3. Enable SSD storgae on overridetree.cb 4. Disable the WFC i2c devcie by fw config BUG=b:259211172 TEST=Build firmware and check the functions on craaskneto/craskino emerge-nissa coreboot chromeos-booimage Change-Id: I6b9c90abe562768ea2afff5608a8cfac764569d5 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craask/fw_config.c M src/mainboard/google/brya/variants/craask/gpio.c M src/mainboard/google/brya/variants/craask/overridetree.cb 3 files changed, 162 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/69693/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/69693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9c90abe562768ea2afff5608a8cfac764569d5 Gerrit-Change-Number: 69693 Gerrit-PatchSet: 7 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: lib/fmap.c: Show error on fmd flash size mismatch with Kconfig
by Martin L Roth (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Shelley Chen, Tarun Tuli, Subrata Banik, Julius Werner, Arthur Heymans. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69486 ) Change subject: lib/fmap.c: Show error on fmd flash size mismatch with Kconfig ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69486/comment/97cd486f_d89cc0bb PS1, Line 14: in helping to eliminate the confusion. > Not really sure what more there needs to be done, I think this should report the problem reliably? I don't remember what I was thinking of when I wrote it. Removed. Patchset: PS1: > On Herobrine there's a weird situation where some of the early test boards were built by Qualcomm wi […] Thanks for the explanation and example. File src/lib/fmap.c: https://review.coreboot.org/c/coreboot/+/69486/comment/4d87d773_a5a6377d PS1, Line 23: #ifdef FMAP_SECTION_FLASH_SIZE > Why would this ever not be defined? We rely on FMAP_OFFSET being available below as well, and this c […] Done https://review.coreboot.org/c/coreboot/+/69486/comment/e84821fb_b3866a6d PS1, Line 25: rom > nit: "ROM" Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ed8e09125567f7c04baca292f102dacee974144 Gerrit-Change-Number: 69486 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 23 Nov 2022 03:51:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Define post codes
by Martin L Roth (Code Review) 23 Nov '22

23 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69865 ) Change subject: soc/intel/common: Define post codes ...................................................................... soc/intel/common: Define post codes For the most part, this just moves the existing post codes into macros so that they're not just bare numbers. cache_as_ram.S: Post code 0x28 was previously pointless with just a single jump between it and post code 0x29, car_init_done. This code was removed, and the 0x28 value was used to differentiate the car_nem_enhanced subroutine from the other 0x26 post codes used before calling the clear_car subroutine. All other post codes remain identical. POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas the POST_SOC codes are expected to be Intel only. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/common/block/cse/cse.c A src/soc/intel/common/block/include/intelblocks/post_codes.h 4 files changed, 72 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 552ba15..1b08af2 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -8,6 +8,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <intelblocks/msr.h> +#include <intelblocks/post_codes.h> .section .init, "ax", @progbits @@ -77,7 +78,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) /* Bootguard sets up its own CAR and needs separate handling */ check_boot_guard: @@ -97,7 +98,7 @@ jmp check_mtrr /* Check if CPU properly reset */ no_reset: - post_code(0x21) + post_code(POST_SOC_NO_RESET) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -110,7 +111,7 @@ wrmsr jnz clear_fixed_mtrr - post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS) /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -128,7 +129,7 @@ dec %ebx jnz clear_var_mtrr - post_code(0x23) + post_code(POST_SOC_CLEAR_VAR_MTRRS) /* Configure default memory type to uncacheable (UC) */ mov $MTRR_DEF_TYPE_MSR, %ecx @@ -156,7 +157,7 @@ bts %eax, %esi dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ - post_code(0x24) + post_code(POST_SOC_SET_UP_CAR_MTRRS) #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) find_free_mtrr @@ -215,7 +216,7 @@ #else #error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing" #endif - post_code(0x25) + post_code(POST_SOC_BOOTGUARD_SETUP) is_bootguard_nem jz no_bootguard_car_continue @@ -267,7 +268,7 @@ .global car_init_done car_init_done: - post_code(0x29) + post_code(POST_SOC_CAR_INIT_DONE) /* Setup bootblock stack */ mov $_ecar_stack, %esp @@ -294,7 +295,7 @@ #endif before_carstage: - post_code(0x2a) + post_code(POST_SOC_BEFORE_CARSTAGE) call bootblock_c_entry /* Never reached */ @@ -327,11 +328,11 @@ or $0x1, %eax wrmsr - post_code(0x26) + post_code(POST_SOC_CLEARING_CAR) clear_car - post_code(0x27) + post_code(POST_SOC_DISABLE_CACHE_EVICT) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx @@ -339,8 +340,6 @@ or $0x2, %eax wrmsr - post_code(0x28) - jmp car_init_done #elif CONFIG(INTEL_CAR_CQOS) @@ -418,11 +417,11 @@ and %ebx, %eax wrmsr - post_code(0x26) + post_code(POST_SOC_CLEARING_CAR) clear_car - post_code(0x27) + post_code(POST_SOC_DISABLE_CACHE_EVICT) /* Cache is populated. Use mask 1 that will block evicts */ mov $IA32_PQR_ASSOC, %ecx @@ -437,8 +436,6 @@ and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax wrmsr - post_code(0x28) - jmp car_init_done #elif CONFIG(INTEL_CAR_NEM_ENHANCED) @@ -449,7 +446,7 @@ rdmsr or $0x1, %eax wrmsr - post_code(0x26) + post_code(POST_SOC_CAR_NEM_ENHANCED) /* Create n-way set associativity of cache */ xorl %edi, %edi @@ -636,7 +633,7 @@ #endif wrmsr - post_code(0x27) + post_code(POST_SOC_DISABLE_CACHE_EVICT) /* * Enable No-Eviction Mode Run State by setting * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. @@ -647,7 +644,5 @@ orl $0x02, %eax wrmsr - post_code(0x28) - jmp car_init_done #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 173ebf7..0126a12 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -3,6 +3,7 @@ #include <device/pci_def.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> +#include <intelblocks/post_codes.h> #define CBFS_FILE_MAGIC 0 #define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) @@ -19,7 +20,7 @@ .global cache_as_ram cache_as_ram: - post_code(0x21) + post_code(POST_BOOTBLOCK_CAR) movl $(CONFIG_FSP_T_LOCATION), %ebx add $0x94, %ebx diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ceb75e2..c2d4484 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> +#include <intelblocks/post_codes.h> #include <option.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> @@ -611,7 +612,7 @@ uint32_t csr; /* Clear post code to prevent eventlog entry from unknown code. */ - post_code(0); + post_code(POST_CODE_ZERO); /* Send reset request */ csr = read_host_csr(); diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h new file mode 100644 index 0000000..d7c0ef1 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_POST_CODES_H +#define SOC_INTEL_COMMON_BLOCK_POST_CODES_H + +/* common/block/cpu/car/cache_as_ram.s */ +#define POST_BOOTBLOCK_PRE_C_ENTRY 0x20 +#define POST_SOC_NO_RESET 0x21 +#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 +#define POST_SOC_CLEAR_VAR_MTRRS 0x23 +#define POST_SOC_SET_UP_CAR_MTRRS 0x24 +#define POST_SOC_BOOTGUARD_SETUP 0x25 +#define POST_SOC_CLEARING_CAR 0x26 +#define POST_SOC_DISABLE_CACHE_EVICT 0x27 +#define POST_SOC_CAR_NEM_ENHANCED 0x28 +#define POST_SOC_CAR_INIT_DONE 0x29 +#define POST_SOC_BEFORE_CARSTAGE 0x2a + +/* common/block/cpu/car/cache_as_ram_fsp.S */ +#define POST_BOOTBLOCK_CAR 0x21 + +/* common/block/cse/cse.c */ +#define POST_CODE_ZERO 0x00 +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab Gerrit-Change-Number: 69865 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/release/build-release: Fix style issues
by Martin L Roth (Code Review) 23 Nov '22

23 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67319 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/release/build-release: Fix style issues ...................................................................... util/release/build-release: Fix style issues No real functional changes, just cleaning up shellcheck issues, putting braces around variables, add comments and the like. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I6e79afc8d725e86ddbf7f4eb4685bed190c20738 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67319 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/release/build-release 1 file changed, 45 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/util/release/build-release b/util/release/build-release index f609bf1..ab0231e 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -12,7 +12,8 @@ set -e if [ -z "$GPG_TTY" ]; then - export GPG_TTY=$(tty) + GPG_TTY=$(tty) + export GPG_TTY fi # set local + tz to be reproducible @@ -21,7 +22,7 @@ TZ=UTC0 export LC_ALL LANG TZ -if [ -z "$VERSION_NAME" ] || [ "$VERSION_NAME" = "--help" ] || [ -z "$COMMIT_ID" ]; then +if [ -z "${VERSION_NAME}" ] || [ "${VERSION_NAME}" = "--help" ] || [ -z "${COMMIT_ID}" ]; then echo "usage: $0 <version> <commit id> [username] [gpg key id]" echo "Tags a new coreboot version and creates a tar archive" echo @@ -39,7 +40,9 @@ exit 1 fi -if [ ! -d "coreboot-${VERSION_NAME}" ]; then +# Clone new copy of repo if needed +if [ ! -d "coreboot-${VERSION_NAME}/.git" ]; then + rm -rf "coreboot-${VERSION_NAME}" declare -a GIT_REF_OPTS if [ -d .git ]; then GIT_REF_OPTS=("--reference" "." "--dissociate") @@ -53,29 +56,31 @@ fi fi -cd "coreboot-${VERSION_NAME}" || exit 1 -if [ -n "$COMMIT_ID" ]; then - git reset --hard "$COMMIT_ID" -fi +# Handle everything that needs to be done from inside the new coreboot +# directory. Use requested version, update submodules, and get ready to +# run from outside a git repository, and create a signed tag to push. +( + cd "coreboot-${VERSION_NAME}" || exit 1 + if [ -n "${COMMIT_ID}" ]; then + git reset --hard "${COMMIT_ID}" + fi -util/crossgcc/buildgcc -W > .crossgcc-version + util/crossgcc/buildgcc -W > .crossgcc-version -git submodule update --init --checkout -if [ -n "$GPG_KEY_ID" ]; then - git tag -a -s -u "$GPG_KEY_ID" --force "$VERSION_NAME" -m "coreboot version $VERSION_NAME" -else - git tag -a --force "$VERSION_NAME" -m "coreboot version $VERSION_NAME" -fi + git submodule update --init --checkout + if [ -n "${GPG_KEY_ID}" ]; then + git tag -a -s -u "$GPG_KEY_ID" --force "${VERSION_NAME}" -m "coreboot version ${VERSION_NAME}" -- + else + git tag -a --force "${VERSION_NAME}" -m "coreboot version ${VERSION_NAME}" -- + fi -printf "%s-%s\n" "$VERSION_NAME" "$(git log --pretty=%h -1)" > .coreboot-version -tstamp=$(git log --pretty=format:%ci -1) -cd .. + printf "%s-%s\n" "$VERSION_NAME" "$(git log --pretty=%h -1)" > .coreboot-version +) -exclude_paths="3rdparty/blobs " -exclude_paths+="3rdparty/fsp " -exclude_paths+="3rdparty/intel-microcode " -exclude_paths+="3rdparty/amd_blobs " -exclude_paths+="3rdparty/qc_blobs " +tstamp=$(tr "-" " " < "coreboot-${VERSION_NAME}/.coreboot-version") + +# Create the two tarballs, source and blobs. +exclude_paths="3rdparty/blobs 3rdparty/fsp 3rdparty/intel-microcode 3rdparty/amd_blobs 3rdparty/qc_blobs" declare -a blobs_paths declare -a exclude_opts @@ -87,6 +92,7 @@ tar --sort=name --mtime="${tstamp}" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore "${exclude_opts[@]}" -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" tar --sort=name --mtime="${tstamp}" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore -cvf - "${blobs_paths[@]}" |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" +# Sign the tarballs if [ -n "${GPG_KEY_ID}" ]; then gpg --armor --local-user "$GPG_KEY_ID" --output "coreboot-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-${VERSION_NAME}.tar.xz" gpg --armor --local-user "$GPG_KEY_ID" --output "coreboot-blobs-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-blobs-${VERSION_NAME}.tar.xz" -- To view, visit https://review.coreboot.org/c/coreboot/+/67319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e79afc8d725e86ddbf7f4eb4685bed190c20738 Gerrit-Change-Number: 67319 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cpu/intel/car: Define post codes
by Martin L Roth (Code Review) 23 Nov '22

23 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69866 ) Change subject: cpu/intel/car: Define post codes ...................................................................... cpu/intel/car: Define post codes This moves a lot of post code values, but unifies them between platforms, so that the same value means the same thing as much as possible. The P4-netburst code was the most extensive and most different, so that dictated the majority of the values. Three were two values there that didn't match the other files, so those two values, 0x22 & 0x29 have duplicate entries in the table. The rest of the entries are similar between platforms, though the values for many of them were moved to match the P4-netburst values. POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become global, while POST_SOC would be specific to the Intel platforms. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69866 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S A src/include/cpu/intel/post_codes.h 7 files changed, 112 insertions(+), 49 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index f47ba5f..fffe3f8 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/intel/post_codes.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -15,7 +16,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -28,7 +29,7 @@ bt $12, %eax jc wait_for_sipi - post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -57,7 +58,7 @@ dec %ebx jnz clear_var_mtrr - post_code(0x22) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -82,7 +83,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) + post_code(POST_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -90,7 +91,7 @@ xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -98,7 +99,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -126,7 +127,7 @@ shr $2, %ecx rep stosl - post_code(0x26) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -145,7 +146,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -179,7 +180,7 @@ #endif before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 0451bb4..2ac660c 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/intel/post_codes.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -20,7 +21,7 @@ jmp check_mtrr /* Check if CPU properly reset */ cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -33,14 +34,14 @@ bt $12, %eax jc wait_for_sipi - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Clean-up MTRR_DEF_TYPE_MSR. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr - post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx xor %eax, %eax @@ -86,7 +87,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) + post_code(POST_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl car_mtrr_start, %eax @@ -94,7 +95,7 @@ xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -115,7 +116,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -186,7 +187,7 @@ orl $3, %eax wrmsr - post_code(0x26) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -197,7 +198,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -232,7 +233,7 @@ #endif before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 2834e76..56370f8 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/intel/post_codes.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -12,14 +13,14 @@ chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_POSTCAR_DISABLE_CACHE) /* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x31) + post_code(POST_POSTCAR_DISABLE_DEF_MTRR) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -35,7 +36,7 @@ andl $~1, %eax wrmsr - post_code(0x32) + post_code(POST_POSTCAR_TEARDOWN_DONE) /* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 887bb22..c19fa3c 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/intel/post_codes.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -13,7 +14,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -41,7 +42,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -49,7 +50,7 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x22) + post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax @@ -67,7 +68,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x2a) + post_code(POST_SOC_SET_CAR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -83,7 +84,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -91,7 +92,7 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr - post_code(0x2c) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax @@ -113,7 +114,7 @@ xorl %eax, %eax rep stosl - post_code(0x2d) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -132,7 +133,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2e) + post_code(POST_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -155,7 +156,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 9ac9e22..01abdf8 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/intel/post_codes.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -19,7 +20,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) movl $LAPIC_BASE_MSR, %ecx rdmsr @@ -52,7 +53,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -60,7 +61,7 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x22) + post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) /* Determine CPU_ADDR_BITS and load PHYSMASK high * word to %edx. @@ -104,7 +105,7 @@ bsp_init: - post_code(0x23) + post_code(POST_SOC_BSP_INIT) /* Send INIT IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -118,7 +119,7 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b - post_code(0x24) + post_code(POST_SOC_COUNT_CORES) movl $1, %eax cpuid @@ -153,7 +154,7 @@ hyper_threading_cpu: - post_code(0x25) + post_code(POST_SOC_CPU_HYPER_THREADING) /* Send Start IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -168,7 +169,7 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b - post_code(0x26) + post_code(POST_SOC_CPU_SIBLING_DELAY) /* Wait for sibling CPU to start. */ 1: movl $(MTRR_PHYS_BASE(0)), %ecx @@ -184,14 +185,14 @@ ap_init: - post_code(0x27) + post_code(POST_SOC_CPU_AP_INIT) /* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - post_code(0x28) + post_code(POST_SOC_SET_MTRR_BASE) /* MTRR registers are shared between HT siblings. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -199,7 +200,7 @@ xorl %edx, %edx wrmsr - post_code(0x29) + post_code(POST_SOC_AP_HALT) ap_halt: cli @@ -210,7 +211,7 @@ sipi_complete: - post_code(0x2a) + post_code(POST_SOC_SET_CAR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -226,7 +227,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -269,7 +270,7 @@ wrmsr no_msr_11e: - post_code(0x2c) + post_code(POST_SOC_ENABLE_CACHE) /* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx @@ -296,7 +297,7 @@ jmp update_bsp_microcode end_microcode_update: #endif - post_code(0x2d) + post_code(POST_SOC_DISABLE_CACHE) /* Disable caching to change MTRR's. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -336,7 +337,7 @@ wrmsr fill_cache: - post_code(0x2e) + post_code(POST_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -379,7 +380,7 @@ #endif before_c_entry: - post_code(0x2f) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 108342f..1684407 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/intel/post_codes.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -10,14 +11,14 @@ chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_POSTCAR_DISABLE_CACHE) /* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x31) + post_code(POST_POSTCAR_DISABLE_DEF_MTRR) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -25,7 +26,7 @@ andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x32) + post_code(POST_POSTCAR_TEARDOWN_DONE) /* Return to caller. */ jmp *%esp diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h new file mode 100644 index 0000000..3db0aeb --- /dev/null +++ b/src/include/cpu/intel/post_codes.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CPU_INTEL_CAR_POST_CODES_H +#define CPU_INTEL_CAR_POST_CODES_H + +#define POST_BOOTBLOCK_CAR 0x20 +#define POST_SOC_SET_DEF_MTRR_TYPE 0x21 +#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate +#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 +#define POST_SOC_BSP_INIT 0x23 +#define POST_SOC_COUNT_CORES 0x24 +#define POST_SOC_CPU_HYPER_THREADING 0x25 +#define POST_SOC_CPU_SIBLING_DELAY 0x26 +#define POST_SOC_CPU_AP_INIT 0x27 +#define POST_SOC_SET_MTRR_BASE 0x28 +#define POST_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate +#define POST_SOC_AP_HALT 0x29 +#define POST_SOC_SET_CAR_BASE 0x2a +#define POST_SOC_ENABLE_MTRRS 0x2b +#define POST_SOC_ENABLE_CACHE 0x2c +#define POST_SOC_DISABLE_CACHE 0x2d +#define POST_SOC_FILL_CACHE 0x2e +#define POST_BOOTBLOCK_BEFORE_C_ENTRY 0x2f + +#define POST_POSTCAR_DISABLE_CACHE 0x30 +#define POST_POSTCAR_DISABLE_DEF_MTRR 0x31 +#define POST_POSTCAR_TEARDOWN_DONE 0x32 + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9 Gerrit-Change-Number: 69866 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: lint/checkpatch: Add XA_STATE and XA_STATE_ORDER to the macro declara...
by Martin L Roth (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67338 ) Change subject: lint/checkpatch: Add XA_STATE and XA_STATE_ORDER to the macro declaration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica20264d744ea8f77b56c63d29e1fafc2e68a869 Gerrit-Change-Number: 67338 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 23 Nov 2022 03:46:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros
by Eric Lai (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Elyes Haouas. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69878 ) Change subject: sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id281a3478051c4876ccbe26452d8744769c86654 Gerrit-Change-Number: 69878 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 23 Nov 2022 03:35:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: sb/intel/i82801gx/lpc.c: Use post_code()
by Eric Lai (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Arthur Heymans, Elyes Haouas. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69901 ) Change subject: sb/intel/i82801gx/lpc.c: Use post_code() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Gerrit-Change-Number: 69901 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 23 Nov 2022 03:34:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: WIP:mb/amd/birman: Split the amdfw.rom into head and body
by Bao Zheng (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69922 to review the following change. Change subject: WIP:mb/amd/birman: Split the amdfw.rom into head and body ...................................................................... WIP:mb/amd/birman: Split the amdfw.rom into head and body Change-Id: I9d61d707c8292f7d89db5fccc26e860ff76e7374 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/birman/board.fmd M src/soc/amd/morgana/Makefile.inc 2 files changed, 43 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/69922/1 diff --git a/src/mainboard/amd/birman/board.fmd b/src/mainboard/amd/birman/board.fmd index 6c6ad92..21a86c0 100644 --- a/src/mainboard/amd/birman/board.fmd +++ b/src/mainboard/amd/birman/board.fmd @@ -1,8 +1,9 @@ -FLASH@0xFF000000 16M { +FLASH@0xFE000000 32M { BIOS { EC 4K + AMDFW(CBFS) @131008 + FMAP @16M 3K RW_MRC_CACHE 120K - FMAP 4K - COREBOOT(CBFS) + COREBOOT(CBFS) @17M } } diff --git a/src/soc/amd/morgana/Makefile.inc b/src/soc/amd/morgana/Makefile.inc index a88e1a5..bbf8cf2 100644 --- a/src/soc/amd/morgana/Makefile.inc +++ b/src/soc/amd/morgana/Makefile.inc @@ -66,13 +66,16 @@ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+ -$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) +MORGANA_FWM_POSITION_REL=$(call _toint, 0x20000) +MORGANA_FWM_POSITION_BODY=$(call _toint, 0x1000) -MORGANA_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +AMDFW_REGION_POSITION=$(call int-subtract, \ + $(shell awk '$$2 == "FMAP_SECTION_AMDFW_START" {print $$3}' $(obj)/fmap_config.h) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + +COREBOOT_REGION_POSITION=$(call int-subtract, \ + $(shell awk '$$2 == "FMAP_SECTION_COREBOOT_START" {print $$3}' $(obj)/fmap_config.h) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough @@ -259,8 +262,10 @@ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ - --location $(shell printf "%#x" $(MORGANA_FWM_POSITION)) \ - --output $@ + --location $(shell printf "%#x" $(MORGANA_FWM_POSITION_REL)) \ + --body-location $(shell printf "%#x" $(call int-add, $(COREBOOT_REGION_POSITION) $(MORGANA_FWM_POSITION_BODY))) \ + --output $@ \ + --body-output "build/body.rom" $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @@ -282,6 +287,12 @@ --anywhere \ --output $@ +regions-for-file = $(subst $(spc),$(comma),$(sort \ + $(if $(value regions-for-file-$(1)), \ + $(regions-for-file-$(1)), \ + ,COREBOOT,\ + ))) + $(obj)/amdfw_b.rom: $(obj)/amdfw.rom rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -296,6 +307,16 @@ --anywhere \ --output $@ +regions-for-file-apu/amdfw=AMDFW +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(call int-subtract, $(MORGANA_FWM_POSITION_REL) $(AMDFW_REGION_POSITION)) +apu/amdfw-type := raw + +cbfs-files-y += apu/amdfwbody +apu/amdfwbody-file := $(obj)/body.rom +apu/amdfwbody-position := $(MORGANA_FWM_POSITION_BODY) +apu/amdfwbody-type := raw ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a -- To view, visit https://review.coreboot.org/c/coreboot/+/69922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d61d707c8292f7d89db5fccc26e860ff76e7374 Gerrit-Change-Number: 69922 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: /: Remove unnecessary space in log messages
by Yu-Ping Wu (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Julius Werner, Elyes Haouas. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69903 ) Change subject: /: Remove unnecessary space in log messages ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69903/comment/0eb92919_4f85fc4f PS1, Line 7: /: Remove unnecessary space in log messages The space is actually not *in* the log messages. How about `Remove extra space after comma`? -- To view, visit https://review.coreboot.org/c/coreboot/+/69903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Gerrit-Change-Number: 69903 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 23 Nov 2022 03:31:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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