coreboot-gerrit November 2022

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[M] Change in coreboot[master]: mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size
by Derek Huang (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Jamie Chen, Stanley Wu, Marco Chen. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69925 ) Change subject: mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69925/comment/f0ab56c4_d0ac43ef PS2, Line 7: Add memory ram id=3 to 8GB size Implement variant_memory_sku() https://review.coreboot.org/c/coreboot/+/69925/comment/5630116e_9ab9d8c7 PS2, Line 9: Add RAM ID=3 define to 8GB size same as RAM ID 1. This change override memory ID 3 to 1 to workaround the incorrect memory straps in hardware. File src/mainboard/google/octopus/variants/phaser/memory.c: https://review.coreboot.org/c/coreboot/+/69925/comment/0aa71f93_87010833 PS2, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2017 Intel Corp. : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ /* SPDX-License-Identifier: GPL-2.0-or-later */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36ec6bad7096e5de666ac6500c8419fc6e383ae1 Gerrit-Change-Number: 69925 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 07:14:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by EricKY Cheng (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Tim Van Patten, Eric Peers, Jason Glenesk, Dtrain Hsu, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 60: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68471/comment/0f296e13_d818cd8e PS60, Line 14: mode. > Possible unwrapped commit description (prefer a maximum 72 chars per line) Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 60 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Nov 2022 07:13:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [For Test] crossgcc: Update GCC from 11.2 to 12.2
by Felix Singer (Code Review) 23 Nov '22

23 Nov '22

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67821 ) Change subject: [For Test] crossgcc: Update GCC from 11.2 to 12.2 ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Do you want to pursue this? v12 adds -Oz which might be an interesting option for coreboot over -Os There is CB:66920 which is meant to track all the issues and fixes. -- To view, visit https://review.coreboot.org/c/coreboot/+/67821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02d5680929b56ad357c3a010cff7e1540001911 Gerrit-Change-Number: 67821 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 23 Nov 2022 07:10:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [For Test] crossgcc: Update GCC from 11.2 to 12.2
by Arthur Heymans (Code Review) 23 Nov '22

23 Nov '22

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67821 ) Change subject: [For Test] crossgcc: Update GCC from 11.2 to 12.2 ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Do you want to pursue this? v12 adds -Oz which might be an interesting option for coreboot over -Os -- To view, visit https://review.coreboot.org/c/coreboot/+/67821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02d5680929b56ad357c3a010cff7e1540001911 Gerrit-Change-Number: 67821 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 23 Nov 2022 07:03:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Adding cros_gpios to rex
by Subrata Banik (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69924 ) Change subject: mb/google/rex: Adding cros_gpios to rex ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieac1df805c6399aefdc13aae136630d496aacd58 Gerrit-Change-Number: 69924 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 07:00:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size
by Stanley Wu (Code Review) 23 Nov '22

23 Nov '22

Stanley Wu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/69925 ) Change subject: mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size ...................................................................... mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size Add RAM ID=3 define to 8GB size same as RAM ID 1. BUG=b:259301885 BRANCH=Octopus TEST=Verified on Phaser Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Change-Id: I36ec6bad7096e5de666ac6500c8419fc6e383ae1 --- M src/mainboard/google/octopus/variants/phaser/Makefile.inc A src/mainboard/google/octopus/variants/phaser/memory.c 2 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/69925/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36ec6bad7096e5de666ac6500c8419fc6e383ae1 Gerrit-Change-Number: 69925 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by EricKY Cheng (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Tim Van Patten, Eric Peers, Jason Glenesk, Dtrain Hsu, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 60: (2 comments) File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/a1484b6b_80ab1549 PS59, Line 22: /* If _SB.DTTS is not present, DTTS is not enabled. */ : If (CondRefOf (\_SB.DTTS)) : { : \_SB.DTTS() : Return (Zero) : } > This needs to be moved down to ref1. Thanks your suggestion. I have moved DTTS region down to ref1. Please help to review it. https://review.coreboot.org/c/coreboot/+/68471/comment/f4c0375e_c17cf82f PS59, Line 52: > ref1 Thanks your suggestion. I have moved DTTS region down to ref1. Please help to review it. -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 60 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Nov 2022 06:46:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size
by build bot (Jenkins) (Code Review) 23 Nov '22

23 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69925 ) Change subject: mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size ...................................................................... Patch Set 1: (15 comments) File src/mainboard/google/octopus/variants/phaser/memory.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/4a45244d_ccd2209e PS1, Line 24: size_t rt; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/4e3d9995_0be6498e PS1, Line 24: size_t rt; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/e56b25d3_49f6d01d PS1, Line 25: gpio_t pads[] = { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/ba6eb632_b802a0c4 PS1, Line 25: gpio_t pads[] = { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/9adbc38f_ff0173ce PS1, Line 26: [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/ffb013c0_79b87357 PS1, Line 26: [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/9d0729d9_2ee5ce6b PS1, Line 27: [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/a9f05cce_852cd22b PS1, Line 27: [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/ceed1dbe_9e4bdb88 PS1, Line 28: }; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/4997532d_f3462e28 PS1, Line 28: }; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/ce62d6a8_fe0d3c32 PS1, Line 30: rt = gpio_base2_value(pads, ARRAY_SIZE(pads)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/02323fbe_67d94227 PS1, Line 30: rt = gpio_base2_value(pads, ARRAY_SIZE(pads)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/e978d2d9_b3f13653 PS1, Line 31: return (rt == 3) ? 1 : rt; // If RAM ID = 3, return 1 code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/c7ff05c5_05fbea1b PS1, Line 31: return (rt == 3) ? 1 : rt; // If RAM ID = 3, return 1 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164356): https://review.coreboot.org/c/coreboot/+/69925/comment/8cdf12a8_170c1324 PS1, Line 32: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/69925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36ec6bad7096e5de666ac6500c8419fc6e383ae1 Gerrit-Change-Number: 69925 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Nov 2022 06:35:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size
by Stanley Wu (Code Review) 23 Nov '22

23 Nov '22

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69925 ) Change subject: mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size ...................................................................... mb/google/octopus/variants/phaser: Add memory ram id=3 to 8GB size Add RAM ID=3 define to 8GB size same as RAM ID 1. BUG=b:259301885 BRANCH=Octopus TEST=Verified on Phaser Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Change-Id: I36ec6bad7096e5de666ac6500c8419fc6e383ae1 --- M src/mainboard/google/octopus/variants/phaser/Makefile.inc A src/mainboard/google/octopus/variants/phaser/memory.c 2 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/69925/1 diff --git a/src/mainboard/google/octopus/variants/phaser/Makefile.inc b/src/mainboard/google/octopus/variants/phaser/Makefile.inc index 37270eb..22ef41c 100644 --- a/src/mainboard/google/octopus/variants/phaser/Makefile.inc +++ b/src/mainboard/google/octopus/variants/phaser/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += variant.c ramstage-y += gpio.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/octopus/variants/phaser/memory.c b/src/mainboard/google/octopus/variants/phaser/memory.c new file mode 100644 index 0000000..04c314f --- /dev/null +++ b/src/mainboard/google/octopus/variants/phaser/memory.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <variant/gpio.h> + +size_t variant_memory_sku(void) +{ + size_t rt; + gpio_t pads[] = { + [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, + [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, + }; + + rt = gpio_base2_value(pads, ARRAY_SIZE(pads)); + return (rt == 3) ? 1 : rt; // If RAM ID = 3, return 1 +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/69925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36ec6bad7096e5de666ac6500c8419fc6e383ae1 Gerrit-Change-Number: 69925 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: commonlib/fsp_relocate.c: Fix cbfstool build on 32-bit host
by Werner Zeh (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Martin L Roth, Paul Menzel, Ed Sharma, Angel Pons. Hello build bot (Jenkins), Martin L Roth, Paul Menzel, Ed Sharma, Mario Scheithauer, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69682 to look at the new patch set (#3). Change subject: commonlib/fsp_relocate.c: Fix cbfstool build on 32-bit host ...................................................................... commonlib/fsp_relocate.c: Fix cbfstool build on 32-bit host On a 32-bit host, uintptr_t is defined as 'unsigned int' instead of 'unsigend long int' like on a 64-bit host. When cbfstool is built on a 32-bit host, the printk format specifier '%lx' expects a 'long int' while new_addr is of type 'uintptr_t', aka 'unsigned int'. This in the end leads to a build error. To fix this and make it build on both, 32- and 64-bit hosts, use PRIxPTR as the format specifier. This macro will be resolved at compile time in the right way on both, 32- and 64-bit hosts. Test=Build cbfstool on 32- and 64-bit hosts. Change-Id: Ia917d2ed31778f3a29c0a6c7368f74c15319b099 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/commonlib/fsp_relocate.c 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/69682/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia917d2ed31778f3a29c0a6c7368f74c15319b099 Gerrit-Change-Number: 69682 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ed Sharma <aeddiesharma(a)fb.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ed Sharma <aeddiesharma(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022