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Change subject: soc/amd/mendocino: Update XHCI GPE to use constant
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69916/comment/31aefe1b_136986f4
PS2, Line 10: This commit changes
This is redundant, and imperative mood could be used.
> …, so change existing code over to use ….
https://review.coreboot.org/c/coreboot/+/69916/comment/7037349d_d1c79d11
PS2, Line 9: The GPE number used for XHCI has now been defined
: in AMD's common code.
Please reference the commit.
https://review.coreboot.org/c/coreboot/+/69916/comment/4e1633ba_67140f30
PS2, Line 9: The GPE number used for XHCI has now been defined
: in AMD's common code. This commit changes over existing
: code to use this new definition.
Please reflow for 72 characters per line. (It fits in two lines.)
File src/soc/amd/common/block/xhci/elog.c:
https://review.coreboot.org/c/coreboot/+/69916/comment/87a29e07_4d09a3af
PS2, Line 56: switch (protocol->major_rev) {
This seems like a separate bug fix. Please split it into a separate commit.
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Change subject: soc/intel/meteorlake: Rename method is_eom to is_manuf_mode
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/me.c:
https://review.coreboot.org/c/coreboot/+/69698/comment/f6942b7b_c9856455
PS1, Line 79: is_manuf_mode
> Kapil, Hmm..I miss the negation. But, is_manuf_mode() naming has no meaning. […]
If not specified (enabled/disabled) it is always considered as enabled.
This is an effort to minimize the difference between ADL & MTL implementations so that later we can move most of the code to the common code.
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Change subject: commonlib/fsp_relocate.c: Fix cbfstool build on 32-bit host
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Patch Set 3: Code-Review+2
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Change subject: util/cbmem: Provide a way to override coreboot path
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/meteorlake: Decouple HECI disabling interface from its Kconfig
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Patch Set 1: Code-Review+2
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Jim Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69929 )
Change subject: drivers/intel/mipi_camera: Remove IPU ES support entry for RPL
......................................................................
drivers/intel/mipi_camera: Remove IPU ES support entry for RPL
The current IPU ES entry value is always set to true for RPL and
kernel picks the ES version of the main IPU FW even for the production
bootloader but loading is not successful due to the authentication
failure.
On Raptor Lake silicon, the production binaries are backward
compatible with ES parts.
This change removes the IPU ES support ACPI entry since the
kernel needs to load the production IPU main firmware on both the
ES/QS parts.
BUG=b:258125833
TEST=Verify the Camera functionality by enabling the IPU secure mode
on RPL variants with both ES/QS silicon.
Signed-off-by: Jim Lai <jim.lai(a)intel.com>
Change-Id: I9fd8ea0dd6ffdb16961bb017ba4388bf99e4d5bc
---
M src/drivers/intel/mipi_camera/camera.c
1 file changed, 26 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/69929/1
diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 5b69c01..ec89971 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -138,9 +138,7 @@
port_name[i] = strdup(name);
if (CONFIG(ACPI_ADL_IPU_ES_SUPPORT)) {
u32 cpu_id = cpu_get_cpuid();
- if (cpu_id == CPUID_ALDERLAKE_J0 || cpu_id == CPUID_ALDERLAKE_Q0 ||
- cpu_id == CPUID_RAPTORLAKE_P_J0 ||
- cpu_id == CPUID_RAPTORLAKE_P_Q0)
+ if (cpu_id == CPUID_ALDERLAKE_J0 || cpu_id == CPUID_ALDERLAKE_Q0)
acpi_dp_add_integer(dsd, "is_es", 1);
else
acpi_dp_add_integer(dsd, "is_es", 0);
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Change subject: mb/google/octopus/variants/phaser: Implement variant_memory_sku()
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/octopus/variants/phaser/memory.c:
https://review.coreboot.org/c/coreboot/+/69925/comment/da541e25_0743a691
PS3, Line 18: return (rt == 3) ? 1 : rt; // If RAM ID = 3, return 1
> the benefit is if HW correct the board after, you don't have to modify the code again.
agree to add board id check to override memory ID for specific board id
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Change subject: util/crossgcc: Limit LLVM targets to the needed ones
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> > Seems not really necessary to me since the Clang toolchain includes all architectures. […]
What kind of metrics are you looking for?
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Change subject: /: Remove extra space after comma
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Patch Set 2: Code-Review+2
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