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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69883 )
Change subject: soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2
......................................................................
Patch Set 12:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69883/comment/fa44065e_9d588de2
PS12, Line 10: - Select DISPLAY_FSP_VERSION_INFO_2 for Meteor Lake soc to
config for
https://review.coreboot.org/c/coreboot/+/69883/comment/98e47671_686b0172
PS12, Line 10: DISPLAY_FSP_VERSION_INFO_2
use `` around
https://review.coreboot.org/c/coreboot/+/69883/comment/cc84c117_bf713d08
PS12, Line 10: soc
SoC
https://review.coreboot.org/c/coreboot/+/69883/comment/50d6bd1e_a92be065
PS12, Line 11: use new header file
some of it may fit itself into the previous line
https://review.coreboot.org/c/coreboot/+/69883/comment/fce8a5fa_c18fb836
PS12, Line 14: Verify
Verified
https://review.coreboot.org/c/coreboot/+/69883/comment/2b1126bc_acde83f0
PS12, Line 14: MTL Rex0
Google/Rex
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Change subject: vc/intel/fsp/mtl: Add new header file FirmwareVersionInfo.h
......................................................................
Patch Set 17:
(2 comments)
File src/vendorcode/intel/fsp/fsp2_0/meteorlake/FirmwareVersionInfo.h:
https://review.coreboot.org/c/coreboot/+/69882/comment/c1424e25_fbe1e1e0
PS17, Line 13: **/
/** @file
Header file for Firmware Version Information
@copyright
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License which accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
https://review.coreboot.org/c/coreboot/+/69882/comment/69cc9f79_d9ad7946
PS17, Line 1: /** @file
: Intel Firmware Version Info (FVI) related definitions.
:
: @todo update document/spec reference
:
: Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
: SPDX-License-Identifier: BSD-2-Clause-Patent
:
: @par Specification Reference:
: System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12
: http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.p…
:
: **/
above licensing is not good for open source. Please use the license agreement from the other file
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Change subject: mb/intel/mtlrvp: align directory structure to chrome project
......................................................................
Patch Set 3:
This change is ready for review.
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Change subject: sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
git grep "define.*TCO1_CNT"
src/southbridge/intel/common/pmutil.h:#define TCO1_CNT 0x68
src/southbridge/intel/common/tco.h:#define TCO1_CNT 0x08
The way the offsets are currently used if one big mess.
TCO fixes are part of bigger changeset to replace a lot of inw/out() with bitwise operations in the ACPI PM register space:
https://review.coreboot.org/c/coreboot/+/69760/5/src/southbridge/intel/i828…
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Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Fred Reitberger.
Hello Lance Zhao, build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Arthur Heymans, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69527
to look at the new patch set (#5).
Change subject: ACPI: Use common code for MADT LAPIC NMIs
......................................................................
ACPI: Use common code for MADT LAPIC NMIs
Use the broadcast ID to deliver LINT1 as NMI to all CPUs,
instead of listing individual LAPIC IDs.
Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/amd/cezanne/acpi.c
M src/soc/amd/glinda/acpi.c
M src/soc/amd/mendocino/acpi.c
M src/soc/amd/morgana/acpi.c
M src/soc/amd/picasso/acpi.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/intel/common/block/acpi/acpi.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/madt.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/madt.c
13 files changed, 45 insertions(+), 95 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/69527/5
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Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cmn/cse: API to perform essential CSE operations post EOP
......................................................................
soc/intel/cmn/cse: API to perform essential CSE operations post EOP
This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.
Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.
Additionally, ensures that CSE .final operation is not sending EOP
and other essential operations if the SoC user selects
SOC_INTEL_CSE_SEND_EOP_LATE config.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 54 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/69977/4
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