coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Update GPIO settings
by 9elements QA (Code Review) 21 Oct '22

21 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68481 ) Change subject: mb/google/skyrim/var/frostflow: Update GPIO settings ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129200 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129199 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/129198 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/129197 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/129196 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129195 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/129194 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/129193 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/129192 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/129191 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/129190 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/129189 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129188 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/129187 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/129186 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/129185 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02272801c85a7c30d24c834a840e026225956fb8 Gerrit-Change-Number: 68481 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Oct 2022 22:24:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: introduce and use common soc_uart_ctrlr_info struct
by 9elements QA (Code Review) 21 Oct '22

21 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68530 ) Change subject: soc/amd: introduce and use common soc_uart_ctrlr_info struct ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129183 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129182 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/129181 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/129180 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/129179 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129178 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/129177 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/129176 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/129175 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/129174 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/129173 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/129172 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129171 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/129170 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/129169 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/129168 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id183a3c838c6ad26e264c2a29f3c20b00f10d9be Gerrit-Change-Number: 68530 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 22:07:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/kahlee: use override devicetrees for variants
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Jason Nien, Martin Roth. Hello build bot (Jenkins), Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68634 to look at the new patch set (#3). Change subject: mb/google/kahlee: use override devicetrees for variants ...................................................................... mb/google/kahlee: use override devicetrees for variants This helps with deduplicating the identical parts of the variants' devicetrees. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 --- M src/mainboard/google/kahlee/Kconfig R src/mainboard/google/kahlee/variants/aleena/overridetree.cb A src/mainboard/google/kahlee/variants/baseboard/devicetree.cb R src/mainboard/google/kahlee/variants/careena/overridetree.cb R src/mainboard/google/kahlee/variants/grunt/overridetree.cb R src/mainboard/google/kahlee/variants/liara/overridetree.cb R src/mainboard/google/kahlee/variants/nuwani/overridetree.cb R src/mainboard/google/kahlee/variants/treeya/overridetree.cb 8 files changed, 66 insertions(+), 225 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/68634/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 Gerrit-Change-Number: 68634 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/cbfstool: Add a new mechanism to provide a memory mapped
by Julius Werner (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Nico Huber, Maximilian Brune, Arthur Heymans. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68160 ) Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped ...................................................................... Patch Set 3: (4 comments) File src/soc/intel/common/block/fast_spi/Makefile.inc: https://review.coreboot.org/c/coreboot/+/68160/comment/fdbebbf7_d934b25b PS3, Line 91: $(call int-subtract, $(CONFIG_ROM_SIZE) 0x1000000) Can we factor this term out into a separate variable (e.g. ext_rom_size or something like that)? I think that would make this easier to read. File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/68160/comment/97cdcc45_f4becb8a PS3, Line 317: static int next_window; nit: namespace a bit better since it's a global (e.g. mmap_next_window) https://review.coreboot.org/c/coreboot/+/68160/comment/41d6bfd0_c4ee0141 PS3, Line 338: MMAP_SIZE nit: That's a bit of an odd way to name fields in an array, particularly since these constants are global and not very well namespaced. How about this instead? ``` union { unsigned long int array[3]; struct { unsigned long int flash_base; unsigned long int mmap_base; unsigned long int mmap_size; }; } mmap_args; ``` https://review.coreboot.org/c/coreboot/+/68160/comment/8b5af9cb_428c45df PS3, Line 358: optarg); Note that this will no longer print the full argument because strtok() cuts it into pieces in-place. Not sure if we care. -- To view, visit https://review.coreboot.org/c/coreboot/+/68160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Gerrit-Change-Number: 68160 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 20 Oct 2022 21:44:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/morgana/smi: Update smi definitions for morgana
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68477 ) Change subject: soc/amd/morgana/smi: Update smi definitions for morgana ...................................................................... soc/amd/morgana/smi: Update smi definitions for morgana Update the SMI definitions for morgana per PPR #57396, rev 1.52 Remove references to dropped SMITYPE_XHC2_PME in xhci.c to fix compile errors. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I6a9f05bcc6a6e4c94114ccbd07628629bdfabcba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68477 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/morgana/include/soc/smi.h M src/soc/amd/morgana/xhci.c 2 files changed, 33 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/soc/amd/morgana/include/soc/smi.h b/src/soc/amd/morgana/include/soc/smi.h index b622ee6..5b82a6a 100644 --- a/src/soc/amd/morgana/include/soc/smi.h +++ b/src/soc/amd/morgana/include/soc/smi.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* TODO: Update for Morgana */ - #ifndef AMD_MORGANA_SMI_H #define AMD_MORGANA_SMI_H @@ -87,7 +85,7 @@ #define SMITYPE_AZPME 39 #define SMITYPE_USB_PD_I2C4 40 #define SMITYPE_GPIO_CTL 41 -#define SMITYPE_XHC2_PME 42 +/* 42 Reserved */ #define SMITYPE_ALT_HPET_ALARM 43 #define SMITYPE_FAN_THERMAL 44 #define SMITYPE_ASF_MASTER_SLAVE 45 @@ -104,18 +102,11 @@ #define SMITYPE_XHC0_PME 56 #define SMITYPE_XHC1_PME 57 #define SMITYPE_ACDC_TIMER 58 -/* 59-60 Reserved */ -#define SMITYPE_XHC3_PME 61 -#define SMITYPE_XHC4_PME 62 -#define SMITYPE_CUR_TEMP_STATUS_5 63 +/* 59-63 Reserved */ #define SMITYPE_KB_RESET 64 #define SMITYPE_SLP_TYP 65 #define SMITYPE_AL2H_ACPI 66 -/* 67 Reserved */ -#define SMITYPE_NB_GPP_PME_PULSE 68 -#define SMITYPE_NB_GPP_HP_PULSE 69 -#define SMITYPE_USB_PD_I2C4_INTR2 70 -/* 71 Reserved */ +/* 67-71 Reserved */ #define SMITYPE_GBL_RLS 72 #define SMITYPE_BIOS_RLS 73 #define SMITYPE_PWRBUTTON_DOWN 74 @@ -137,7 +128,7 @@ #define SMITYPE_SHORT_TIMER 142 #define SMITYPE_LONG_TIMER 143 #define SMITYPE_AB_SMI 144 -#define SMITYPE_ANY_RESET 145 +/* 145 Reserved */ #define SMITYPE_ESPI_SMI 146 /* 147 Reserved */ #define SMITYPE_IOTRAP0 148 @@ -158,22 +149,22 @@ #define SMI_REG_SMISTS4 0x90 #define SMI_REG_POINTER 0x94 -# define SMI_STATUS_SRC_SCI (1 << 0) -# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ -# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ -# define SMI_STATUS_SRC_2 (1 << 3) -# define SMI_STATUS_SRC_3 (1 << 4) -# define SMI_STATUS_SRC_4 (1 << 5) +# define SMI_STATUS_SRC_SCI BIT(0) +# define SMI_STATUS_SRC_0 BIT(1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 BIT(2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 BIT(3) +# define SMI_STATUS_SRC_3 BIT(4) +# define SMI_STATUS_SRC_4 BIT(5) #define SMI_TIMER 0x96 #define SMI_TIMER_MASK 0x7fff #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 -# define SMITRIG0_PSP (1 << 25) -# define SMITRG0_EOS (1 << 28) -# define SMI_TIMER_SEL (1 << 29) -# define SMITRG0_SMIENB (1 << 31) +# define SMITRIG0_PSP BIT(25) +# define SMITRG0_EOS BIT(28) +# define SMI_TIMER_SEL BIT(29) +# define SMITRG0_SMIENB BIT(31) #define SMI_REG_CONTROL0 0xa0 #define SMI_REG_CONTROL1 0xa4 diff --git a/src/soc/amd/morgana/xhci.c b/src/soc/amd/morgana/xhci.c index 9f62b18..214618d 100644 --- a/src/soc/amd/morgana/xhci.c +++ b/src/soc/amd/morgana/xhci.c @@ -23,12 +23,6 @@ .gpe = GEVENT_31, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG - }, - { - .scimap = SMITYPE_XHC2_PME, - .gpe = GEVENT_31, - .direction = SMI_SCI_LVL_HIGH, - .level = SMI_SCI_EDG } }; @@ -48,12 +42,6 @@ *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) { - if (dev->path.pci.devfn == XHCI2_DEVFN - && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { - *gpe = xhci_sci_sources[2].gpe; - return CB_SUCCESS; - } } return CB_ERR_ARG; -- To view, visit https://review.coreboot.org/c/coreboot/+/68477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a9f05bcc6a6e4c94114ccbd07628629bdfabcba Gerrit-Change-Number: 68477 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/morgana/smi: Update smi definitions for morgana
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Jason Glenesk, Paul Menzel, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68477 ) Change subject: soc/amd/morgana/smi: Update smi definitions for morgana ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a9f05bcc6a6e4c94114ccbd07628629bdfabcba Gerrit-Change-Number: 68477 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 21:40:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/cezanne/uart: separate data and code
by 9elements QA (Code Review) 20 Oct '22

20 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68527 ) Change subject: soc/amd/cezanne/uart: separate data and code ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129149 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129148 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/129147 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/129146 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/129145 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129144 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/129143 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/129142 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/129141 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/129140 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/129139 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/129138 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129137 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/129136 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/129135 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/129134 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e585370a0de56787340788acfecc7931820566d Gerrit-Change-Number: 68527 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 21:38:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/herobrine: Remove NVMe from device tree
by 9elements QA (Code Review) 20 Oct '22

20 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68571 ) Change subject: mb/google/herobrine: Remove NVMe from device tree ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129132 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129131 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/129130 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/129129 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/129128 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129127 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/129126 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/129125 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/129124 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/129123 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/129122 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/129121 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129120 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/129119 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/129118 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/129117 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I802dd1361bc56a24ab3d65e6782bc611b7b75ee3 Gerrit-Change-Number: 68571 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 21:22:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/google/kahlee: use override devicetrees for variants
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Jason Nien, Martin Roth. Hello Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68634 to look at the new patch set (#2). Change subject: mb/google/kahlee: use override devicetrees for variants ...................................................................... mb/google/kahlee: use override devicetrees for variants This helps with deduplicating the identical parts of the variants' devicetrees. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 --- M src/mainboard/google/kahlee/Kconfig R src/mainboard/google/kahlee/variants/aleena/overridetree.cb A src/mainboard/google/kahlee/variants/baseboard/devicetree.cb R src/mainboard/google/kahlee/variants/careena/overridetree.cb R src/mainboard/google/kahlee/variants/grunt/overridetree.cb R src/mainboard/google/kahlee/variants/liara/overridetree.cb R src/mainboard/google/kahlee/variants/nuwani/overridetree.cb R src/mainboard/google/kahlee/variants/treeya/overridetree.cb 8 files changed, 65 insertions(+), 193 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/68634/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 Gerrit-Change-Number: 68634 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: mb/google/kahlee: use override devicetrees for variants
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68634 ) Change subject: mb/google/kahlee: use override devicetrees for variants ...................................................................... mb/google/kahlee: use override devicetrees for variants This helps with deduplicating the identical parts of the variant's devicetree's. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 --- M src/mainboard/google/kahlee/Kconfig R src/mainboard/google/kahlee/variants/aleena/overridetree.cb A src/mainboard/google/kahlee/variants/baseboard/devicetree.cb R src/mainboard/google/kahlee/variants/careena/overridetree.cb R src/mainboard/google/kahlee/variants/grunt/overridetree.cb R src/mainboard/google/kahlee/variants/liara/overridetree.cb R src/mainboard/google/kahlee/variants/nuwani/overridetree.cb R src/mainboard/google/kahlee/variants/treeya/overridetree.cb 8 files changed, 65 insertions(+), 193 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/68634/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 10524fe..8c8486e 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -64,7 +64,10 @@ default "Treeya" if BOARD_GOOGLE_TREEYA config DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_FAMILY string diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/overridetree.cb similarity index 78% rename from src/mainboard/google/kahlee/variants/aleena/devicetree.cb rename to src/mainboard/google/kahlee/variants/aleena/overridetree.cb index 42c4017..7047598 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" register "stapm_percent" = "80" register "stapm_time_ms" = "2500000" register "stapm_power_mw" = "7800" @@ -41,31 +34,15 @@ .fall_time_ns = 19, }" - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ - GPIO_I2C2_SCL | GPIO_I2C3_SCL" - device domain 0 on - device ref iommu off end # IOMMU (Disabled for performance and battery) - device ref gfx on end - device ref gfx_hda on end - device ref gpp_bridge_1 on end # WLAN device ref gpp_bridge_3 on chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end end - device ref hda_bridge on end - device ref hda on end - device ref xhci on end - device ref ehci on end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device ref sdhci on end end #domain + device ref i2c_0 on chip drivers/generic/adau7002 device generic 0.0 on end @@ -95,14 +72,6 @@ device generic 0.1 on end end end - device ref i2c_1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - device i2c 50 on end - end - end device ref i2c_2 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..0400785 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -0,0 +1,42 @@ + +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/stoneyridge + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" + register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" + register "uma_size" = "32 * MiB" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + device domain 0 on + device ref iommu off end # IOMMU (Disabled for performance and battery) + device ref gfx on end + device ref gfx_hda on end + device ref gpp_bridge_1 on end # WLAN + device ref gpp_bridge_3 on end + device ref hda_bridge on end + device ref hda on end + device ref xhci on end + device ref ehci on end + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref sdhci on end + end #domain + + device ref i2c_1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + device i2c 50 on end + end + end +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/overridetree.cb similarity index 82% rename from src/mainboard/google/kahlee/variants/careena/devicetree.cb rename to src/mainboard/google/kahlee/variants/careena/overridetree.cb index ece7403..82d2b99 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" register "stapm_percent" = "68" register "stapm_time_ms" = "2500000" register "stapm_power_mw" = "7800" @@ -41,31 +34,15 @@ .fall_time_ns = 19, }" - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ - GPIO_I2C2_SCL | GPIO_I2C3_SCL" - device domain 0 on - device ref iommu off end # IOMMU (Disabled for performance and battery) - device ref gfx on end - device ref gfx_hda on end - device ref gpp_bridge_1 on end # WLAN device ref gpp_bridge_3 on chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end end - device ref hda_bridge on end - device ref hda on end - device ref xhci on end - device ref ehci on end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device ref sdhci on end end #domain + device ref i2c_0 on chip drivers/generic/adau7002 register "wakeup_delay" = "20" @@ -111,14 +88,6 @@ device generic 0.1 on end end end - device ref i2c_1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - device i2c 50 on end - end - end device ref i2c_2 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/overridetree.cb similarity index 76% rename from src/mainboard/google/kahlee/variants/grunt/devicetree.cb rename to src/mainboard/google/kahlee/variants/grunt/overridetree.cb index a230e00c..3185c4f 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" register "stapm_percent" = "80" register "stapm_time_ms" = "2500000" register "stapm_power_mw" = "7800" @@ -41,31 +34,15 @@ .fall_time_ns = 50, }" - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ - GPIO_I2C2_SCL | GPIO_I2C3_SCL" - device domain 0 on - device ref iommu off end # IOMMU (Disabled for performance and battery) - device ref gfx on end - device ref gfx_hda on end - device ref gpp_bridge_1 on end # WLAN device ref gpp_bridge_3 on chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end end - device ref hda_bridge on end - device ref hda on end - device ref xhci on end - device ref ehci on end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device ref sdhci on end end #domain + device ref i2c_0 on chip drivers/generic/adau7002 device generic 0.0 on end @@ -95,14 +72,6 @@ device generic 0.1 on end end end - device ref i2c_1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - device i2c 50 on end - end - end device ref i2c_2 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/overridetree.cb similarity index 78% rename from src/mainboard/google/kahlee/variants/liara/devicetree.cb rename to src/mainboard/google/kahlee/variants/liara/overridetree.cb index 34c3fde..c565715 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms @@ -40,31 +33,15 @@ .fall_time_ns = 8, }" - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ - GPIO_I2C2_SCL | GPIO_I2C3_SCL" - device domain 0 on - device ref iommu off end # IOMMU (Disabled for performance and battery) - device ref gfx on end - device ref gfx_hda on end - device ref gpp_bridge_1 on end # WLAN device ref gpp_bridge_3 on chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end end - device ref hda_bridge on end - device ref hda on end - device ref xhci on end - device ref ehci on end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device ref sdhci on end end #domain + device ref i2c_0 on chip drivers/generic/adau7002 register "wakeup_delay" = "20" @@ -95,14 +72,6 @@ device generic 0.1 on end end end - device ref i2c_1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - device i2c 50 on end - end - end device ref i2c_2 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb similarity index 83% rename from src/mainboard/google/kahlee/variants/nuwani/devicetree.cb rename to src/mainboard/google/kahlee/variants/nuwani/overridetree.cb index 894eb9d..adbf594 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" register "stapm_percent" = "80" register "stapm_time_ms" = "2000000" register "stapm_power_mw" = "7800" @@ -44,14 +37,7 @@ .fall_time_ns = 8, }" - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ - GPIO_I2C2_SCL | GPIO_I2C3_SCL" - device domain 0 on - device ref iommu off end # IOMMU (Disabled for performance and battery) - device ref gfx on end - device ref gfx_hda on end - device ref gpp_bridge_1 on end # WLAN device ref gpp_bridge_3 on chip drivers/generic/bayhub register "power_saving" = "1" @@ -59,17 +45,8 @@ device pci 00.0 on end end end - device ref hda_bridge on end - device ref hda on end - device ref xhci on end - device ref ehci on end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device ref sdhci on end end #domain + device ref i2c_0 on chip drivers/generic/adau7002 device generic 0.0 on end @@ -99,14 +76,6 @@ device generic 0.1 on end end end - device ref i2c_1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - device i2c 50 on end - end - end device ref i2c_2 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb similarity index 83% rename from src/mainboard/google/kahlee/variants/treeya/devicetree.cb rename to src/mainboard/google/kahlee/variants/treeya/overridetree.cb index e2f965a..6879ee5 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" register "stapm_percent" = "80" register "stapm_time_ms" = "2000000" register "stapm_power_mw" = "7800" @@ -44,14 +37,7 @@ .fall_time_ns = 8, }" - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ - GPIO_I2C2_SCL | GPIO_I2C3_SCL" - device domain 0 on - device ref iommu off end # IOMMU (Disabled for performance and battery) - device ref gfx on end - device ref gfx_hda on end - device ref gpp_bridge_1 on end # WLAN device ref gpp_bridge_3 on chip drivers/generic/bayhub register "power_saving" = "1" @@ -59,17 +45,8 @@ device pci 00.0 on end end end - device ref hda_bridge on end - device ref hda on end - device ref xhci on end - device ref ehci on end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device ref sdhci on end end #domain + device ref i2c_0 on chip drivers/generic/adau7002 device generic 0.0 on end @@ -114,14 +91,6 @@ device generic 0.1 on end end end - device ref i2c_1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - device i2c 50 on end - end - end device ref i2c_2 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/68634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 Gerrit-Change-Number: 68634 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit October 2022