coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

1 participants
5881 discussions

[M] Change in coreboot[master]: soc/amd/morgana/uart: introduce and use soc_get_uart_ctrlr_info
by 9elements QA (Code Review) 21 Oct '22

21 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68537 ) Change subject: soc/amd/morgana/uart: introduce and use soc_get_uart_ctrlr_info ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129285 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129284 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/129283 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/129282 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/129281 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129280 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/129279 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/129278 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/129277 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/129276 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/129275 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/129274 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129273 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/129272 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/129271 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/129270 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80278f1a098b389d78f8e9a9fb875c4e466dc5db Gerrit-Change-Number: 68537 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 23:36:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: Create gladios4es RPL variant
by Nick Vaccaro (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Kevin Chiu, Angel Pons, Ricky Chang, Zhuohao Lee. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68570 ) Change subject: mb/google/brya: Create gladios4es RPL variant ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Is the mainboard itself (the PCB) the same (or similar enough) between ADL and RPL? If so, there's n […] Hi Kevin, Intel RPL FSP does currently work for both RPL and ADL (as does CSME). Please see the "Skolas Firmware Plan" document section "RPL SKU of ADL Variant Implementation" for an example of how to support both gladios ADL and gladios RPL in the same image (i.e. gladios RPL becomes a SKU of the gladios ADL variant). Please file a bug and assign to me if more guidance is needed or if you need access to the document. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/68570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic30f7fe30eb0a3151cdf46fff609819056b2fbfe Gerrit-Change-Number: 68570 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Oct 2022 23:36:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: console: Add a 32-bit vendor post-code call
by Julius Werner (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Martin L Roth, Angel Pons, Martin Roth. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68545 ) Change subject: console: Add a 32-bit vendor post-code call ...................................................................... Patch Set 2: (1 comment) File src/console/post.c: https://review.coreboot.org/c/coreboot/+/68545/comment/e2b7944a_bb55828a PS1, Line 22: uint32_t > If you want, I can update it to 8-bit for now, and expand it to 32-bits later as part of the overall redesign. Yeah I think that would be better, then it will make more sense to the reviewers. -- To view, visit https://review.coreboot.org/c/coreboot/+/68545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 Gerrit-Change-Number: 68545 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 23:34:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_info
by 9elements QA (Code Review) 21 Oct '22

21 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68536 ) Change subject: soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_info ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129268 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129267 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/129266 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/129265 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/129264 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129263 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/129262 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/129261 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/129260 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/129259 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/129258 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/129257 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129256 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/129255 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/129254 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/129253 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cfea274f4c9e908c11429199479aec037a00097 Gerrit-Change-Number: 68536 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 23:21:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/cezanne/uart: introduce and use soc_get_uart_ctrlr_info
by 9elements QA (Code Review) 21 Oct '22

21 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68535 ) Change subject: soc/amd/cezanne/uart: introduce and use soc_get_uart_ctrlr_info ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129251 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129250 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/129249 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/129248 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/129247 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129246 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/129245 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/129244 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/129243 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/129242 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/129241 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/129240 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129239 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/129238 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/129237 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/129236 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab1aec44c55570aa8085aeaf68ec69fe6de0f2ba Gerrit-Change-Number: 68535 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 23:12:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake-N: Enable FIVR VCCST ICCMax Control
by Reka Norman (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: V Sowmya, Kangheui Won, Tim Wawrzynczak, Baieswara Reddy Sagili. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68252 ) Change subject: soc/intel/alderlake-N: Enable FIVR VCCST ICCMax Control ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68252/comment/a0b2f8b7_575c94ea PS2, Line 7: alderlake-N nit: maybe alderlake_n? -- To view, visit https://review.coreboot.org/c/coreboot/+/68252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5 Gerrit-Change-Number: 68252 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 23:11:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: console: Add a 32-bit vendor post-code call
by Martin Roth (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Martin L Roth, Julius Werner, Angel Pons. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68545 ) Change subject: console: Add a 32-bit vendor post-code call ...................................................................... Patch Set 2: (1 comment) File src/console/post.c: https://review.coreboot.org/c/coreboot/+/68545/comment/53784421_c8a0951c PS1, Line 22: uint32_t > > One of those patches comes immediately after this, and more are coming. […] You're absolutely right about the following patch, currently it only needs to be 8-bit. Yes, I have some other code that was calling soc_post_code() directly, but it's not ready to post yet. Really, my desire is to update coreboot's entire post-code system, which is kind of a disaster right now in my opinion. I've mentioned this before at a leadership meeting, but I haven't had the time to finish redesigning it. The soc_post_code() function above was part of that redesign that I pulled in for this specific feature. If you want, I can update it to 8-bit for now, and expand it to 32-bits later as part of the overall redesign. -- To view, visit https://review.coreboot.org/c/coreboot/+/68545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 Gerrit-Change-Number: 68545 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 23:07:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
by Reka Norman (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Tim Wawrzynczak. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68553 ) Change subject: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68553/comment/98e22dad_bd338359 PS1, Line 7: for nissa > Please move that into the prefix. Done https://review.coreboot.org/c/coreboot/+/68553/comment/45f0e2bd_b9afbe89 PS1, Line 10: Including the pre-x86 timestamps causes confusion since the boot : time appears to be greater than 1s > Please include the data without and with the patch. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Gerrit-Change-Number: 68553 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 22:59:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
by Reka Norman (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Reka Norman, Tim Wawrzynczak. Hello V Sowmya, build bot (Jenkins), Tarun Tuli, Subrata Banik, Kangheui Won, Tim Wawrzynczak, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68553 to look at the new patch set (#2). Change subject: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY ...................................................................... mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY On nissa, the pre-x86 time is not part of the 1s firmware boot time target. Including the pre-x86 timestamps causes confusion since the boot time appears to be greater than 1s, so disable the Kconfig on nissa. We're not doing any analysis or optimisation of the pre-x86 time on nissa anyway, this work will start from MTL onwards. Also, the Kconfig is already disabled on the brya firmware branch, so this will result in the same behaviour as brya. Before: Total Time: 1,205,840 After: Total Time: 995,300 BUG=b:239769532 TEST=Boot nivviks, check "1st timestamp" is the first timestamp. Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/soc/intel/alderlake/Kconfig 2 files changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/68553/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Gerrit-Change-Number: 68553 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/mendocino: Add code for printing STB to boot log
by build bot (Jenkins) (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68544 ) Change subject: soc/amd/mendocino: Add code for printing STB to boot log ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/mendocino/include/soc/stb.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160923): https://review.coreboot.org/c/coreboot/+/68544/comment/2c7c7aaa_29e69559 PS2, Line 6: #define STB_CFG_SMN_ADDR 0x3E00000 please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/68544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66 Gerrit-Change-Number: 68544 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Oct 2022 22:52:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022