coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: crota/overridetree.cb: Update ELAN's touchscreen delay to 150 ms (per...
by Tarun Tuli (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Paz Zcharya, Subrata Banik, Terry Chen, Tim Wawrzynczak, Nick Vaccaro, Franklin Lin. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68868 ) Change subject: crota/overridetree.cb: Update ELAN's touchscreen delay to 150 ms (per new uploaded datasheet in AVL) ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68868/comment/3a008e2c_51870d18 PS3, Line 7: crota/overridetree.cb: Update ELAN's touchscreen delay to 150 ms (per new uploaded datasheet in AVL) "crota/overridetree.cb:" should probably be "mb/google/brya:" Max line length of all lines in message should be 72 chars Please quote the revision number/date of the updated AVL -- To view, visit https://review.coreboot.org/c/coreboot/+/68868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17e1f7d419637f6dff4049484ce1836ad98017ea Gerrit-Change-Number: 68868 Gerrit-PatchSet: 3 Gerrit-Owner: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Franklin Lin <franklin_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rajat Jain <rajatja(a)google.com> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Franklin Lin <franklin_lin(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 22:23:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update vboot submodule to upstream main
by Julius Werner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jakub Czapiga, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68540 ) Change subject: Update vboot submodule to upstream main ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a16d6e02cee34140ec375ed6166f47560459140 Gerrit-Change-Number: 68540 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 22:21:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/clevo/l140cu: drop System76 EC
by Michael Niewöhner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michal Zygowski. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59816 ) Change subject: mb/clevo/l140cu: drop System76 EC ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/59816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5 Gerrit-Change-Number: 59816 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 22:21:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/clevo/l140cu: make use of the new clevo/it5570e ec driver
by Michael Niewöhner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68795 ) Change subject: mb/clevo/l140cu: make use of the new clevo/it5570e ec driver ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/68795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac401ada2945bb58fe862895458b10fed505fe Gerrit-Change-Number: 68795 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 22:21:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/clevo/l140mu: PECI idle workaround
by Michael Niewöhner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68794 ) Change subject: mb/clevo/l140mu: PECI idle workaround ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/68794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85193000af67cd2c0465bdbb58cdd51b68fd5b4f Gerrit-Change-Number: 68794 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 22:21:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/clevo/l140cu: PECI idle workaround
by Michael Niewöhner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68793 ) Change subject: mb/clevo/l140cu: PECI idle workaround ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/68793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5a6b0ad3553c2cf795037d6a1982102bcb04644 Gerrit-Change-Number: 68793 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 22:21:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/clevo/l140cu: enable S0ix
by Michael Niewöhner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68792 ) Change subject: mb/clevo/l140cu: enable S0ix ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/68792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdf93e1e599e7cc03fc02297eafb49d34b1f6172 Gerrit-Change-Number: 68792 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 22:21:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: ec/clevo/it5570e: add driver for EC used on various Clevo laptops
by Michael Niewöhner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68791 ) Change subject: ec/clevo/it5570e: add driver for EC used on various Clevo laptops ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/68791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8c0bee9002ad9edcd10c83b775fc723744caaa0 Gerrit-Change-Number: 68791 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 22:20:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/gardenia,pademelon: rewrite IRQ mapping handling
by Felix Held (Code Review) 26 Oct '22

26 Oct '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68852 ) Change subject: mb/amd/gardenia,pademelon: rewrite IRQ mapping handling ...................................................................... mb/amd/gardenia,pademelon: rewrite IRQ mapping handling Gardenia and Pademelon had the same mainboard_picr_data and mainboard_intr_data data arrays. Compared to Kahlee there were 4 differences for PIRQ_F, PIRQ_SCI, PIRQ_SD and PIRQ_SATA in the IRQ data arrays. TODO: Verify that the change on Kahlee doesn't break anything there. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia460b467990be7c3e6261440505988a9770ea084 --- M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/pademelon/mainboard.c 2 files changed, 149 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/68852/1 diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 8a4da9f..e4885a6 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -5,63 +5,87 @@ #include <amdblocks/amd_pci_util.h> #include <soc/gpio.h> #include <soc/southbridge.h> +#include <string.h> #include "gpio.h" -/*********************************************************** +/* * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and * IOAPIC IRQs to the different PCI devices on the system. It * is read and written via registers 0xC00/0xC01 as an * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. */ -static const u8 mainboard_picr_data[FCH_IRQ_ROUTING_ENTRIES] = { - [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, - [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, - [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, - [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; + +static const struct fch_irq_routing fch_irq_map[] = { + { PIRQ_A, 3, 16 }, + { PIRQ_B, 4, 17 }, + { PIRQ_C, 5, 18 }, + { PIRQ_D, 7, 19 }, + { PIRQ_E, 11, 20 }, + { PIRQ_F, 10, 21 }, + { PIRQ_G, PIRQ_NC, 22 }, + { PIRQ_H, PIRQ_NC, 23 }, + { PIRQ_SCI, PIRQ_NC, 9 }, + { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC }, + { PIRQ_HDA, 3, 16 }, + { PIRQ_SD, PIRQ_NC, 16 }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_EHCI, 5, 18 }, + { PIRQ_XHCI, 4, 18 }, + { PIRQ_SATA, PIRQ_NC, 19 }, + { PIRQ_GPIO, 7, 7 }, + { PIRQ_I2C0, 3, 3 }, + { PIRQ_I2C1, 15, 15 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 14, 14 }, + { PIRQ_UART0, 10, 10 }, + { PIRQ_UART1, 11, 11 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0xf1, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, }; -static const u8 mainboard_intr_data[FCH_IRQ_ROUTING_ENTRIES] = { - [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, - [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +static void init_tables(void) +{ + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; + } +} /* PIRQ Setup */ static void pirq_setup(void) { - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; } static void mainboard_init(void *chip_info) @@ -77,6 +101,7 @@ *************************************************/ static void mainboard_enable(struct device *dev) { + init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/pademelon/mainboard.c b/src/mainboard/amd/pademelon/mainboard.c index 2e55009..c03febc 100644 --- a/src/mainboard/amd/pademelon/mainboard.c +++ b/src/mainboard/amd/pademelon/mainboard.c @@ -6,57 +6,81 @@ #include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> +#include <string.h> #include "gpio.h" -/*********************************************************** +/* * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and * IOAPIC IRQs to the different PCI devices on the system. It * is read and written via registers 0xC00/0xC01 as an * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. */ -static const u8 mainboard_picr_data[FCH_IRQ_ROUTING_ENTRIES] = { - [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, - [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, - [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, - [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; + +static const struct fch_irq_routing fch_irq_map[] = { + { PIRQ_A, 3, 16 }, + { PIRQ_B, 4, 17 }, + { PIRQ_C, 5, 18 }, + { PIRQ_D, 7, 19 }, + { PIRQ_E, 11, 20 }, + { PIRQ_F, 10, 21 }, + { PIRQ_G, PIRQ_NC, 22 }, + { PIRQ_H, PIRQ_NC, 23 }, + { PIRQ_SCI, PIRQ_NC, 9 }, + { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC }, + { PIRQ_HDA, 3, 16 }, + { PIRQ_SD, PIRQ_NC, 16 }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_EHCI, 5, 18 }, + { PIRQ_XHCI, 4, 18 }, + { PIRQ_SATA, PIRQ_NC, 19 }, + { PIRQ_GPIO, 7, 7 }, + { PIRQ_I2C0, 3, 3 }, + { PIRQ_I2C1, 15, 15 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 14, 14 }, + { PIRQ_UART0, 10, 10 }, + { PIRQ_UART1, 11, 11 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0xf1, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, }; -static const u8 mainboard_intr_data[FCH_IRQ_ROUTING_ENTRIES] = { - [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, - [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +static void init_tables(void) +{ + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; + } +} /* * This table defines the index into the picr/intr_data tables for each @@ -88,8 +112,8 @@ { pirq_data_ptr = mainboard_pirq_data; pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; } static void mainboard_init(void *chip_info) @@ -105,6 +129,7 @@ *************************************************/ static void mainboard_enable(struct device *dev) { + init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/68852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia460b467990be7c3e6261440505988a9770ea084 Gerrit-Change-Number: 68852 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [TESTME] mb/google/kahlee/mainboard: rewrite IRQ mapping handling
by Felix Held (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Nien, Martin Roth. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68851 ) Change subject: [TESTME] mb/google/kahlee/mainboard: rewrite IRQ mapping handling ...................................................................... [TESTME] mb/google/kahlee/mainboard: rewrite IRQ mapping handling Rewrite the Kahlee IRQ mapping handling to be in line with the newer AMD SoCs to allow making the largest part of the corresponding code common for all AMD SoCs in the coreboot tree. The PIC-mode IRQ numbers for both PIRQ_ASF and PIRQ_SDIO were 0 in the data tables which is the PIT IRQ which looks very wrong to me, so it was changed to PIRQ_NC. Since the ASF and likely also the SDIO controller are unused, this shouldn't change runtime behavior. The data tables also had non 0 and non 0x1f entries in the following locations the internal BKDG describes as unused: 0x31-0x33, 0x35-0x37, 0x40, 0x50-0x53 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9 --- M src/mainboard/google/kahlee/mainboard.c 1 file changed, 85 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/68851/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 196d6b8..3433f8b 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -18,55 +18,77 @@ #include <variant/ec.h> #include <variant/thermal.h> -/*********************************************************** +/* * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and * IOAPIC IRQs to the different PCI devices on the system. It * is read and written via registers 0xC00/0xC01 as an * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. */ +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; -static const u8 mainboard_picr_data[FCH_IRQ_ROUTING_ENTRIES] = { - [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F, - [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, - [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, - [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +static const struct fch_irq_routing fch_irq_map[] = { + { PIRQ_A, 3, 16 }, + { PIRQ_B, 4, 17 }, + { PIRQ_C, 5, 18 }, + { PIRQ_D, 7, 19 }, + { PIRQ_E, 11, 20 }, + { PIRQ_F, PIRQ_NC, PIRQ_NC }, + { PIRQ_G, PIRQ_NC, 22 }, + { PIRQ_H, PIRQ_NC, 23 }, + { PIRQ_SCI, 9, 9 }, + { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC }, + { PIRQ_HDA, 3, 16 }, + { PIRQ_SD, 3, 16 }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_EHCI, 5, 18 }, + { PIRQ_XHCI, 4, 18 }, + { PIRQ_SATA, 4, 19 }, + { PIRQ_GPIO, 7, 7 }, + { PIRQ_I2C0, 3, 3 }, + { PIRQ_I2C1, 15, 15 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 14, 14 }, + { PIRQ_UART0, 10, 10 }, + { PIRQ_UART1, 11, 11 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0xf1, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, }; -static const u8 mainboard_intr_data[FCH_IRQ_ROUTING_ENTRIES] = { - [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x1F, 0x16, 0x17, - [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, - [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +static void init_tables(void) +{ + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; + } +} /* * This table defines the index into the picr/intr_data tables for each @@ -95,8 +117,8 @@ { pirq_data_ptr = mainboard_pirq_data; pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; } void __weak variant_devtree_update(void) @@ -143,6 +165,7 @@ *************************************************/ static void mainboard_enable(struct device *dev) { + init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); -- To view, visit https://review.coreboot.org/c/coreboot/+/68851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9 Gerrit-Change-Number: 68851 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2022