coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT
by Nelson Ye (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Paul Menzel, Jon Murphy, Martin Roth, Karthik Ramasubramanian. Nelson Ye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68742 ) Change subject: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68742/comment/6e420045_be887368 PS1, Line 9: thermal table config E > Why E? Hi Paul, Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoid any thermal-related issue during EVT build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A. Thermal config change logic please refer design doc as below. design doc:https://docs.google.com/document/d/1g1L3jnkiA3EsoabQr9YMaEqPYW9IvmbtnJe… -- To view, visit https://review.coreboot.org/c/coreboot/+/68742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76 Gerrit-Change-Number: 68742 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Isaac Lee <isaaclee(a)google.com> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 01:50:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Disable tbt_pcie_rp3 root port
by John Zhao (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68854 ) Change subject: mb/google/rex: Disable tbt_pcie_rp3 root port ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/68854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b Gerrit-Change-Number: 68854 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 01:39:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mem_chip_info: Update to new format
by Julius Werner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68871 ) Change subject: mem_chip_info: Update to new format ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/68871/comment/24b51707_b9f3c71e PS2, Line 132: } @Yu-Ping: I wrote this as a best guess of how I assume it would probably fit together, but I don't know what exactly those MTK structures mean. Can you check if it makes sense like this or if I can adapt it some way to make the densities match up? It would be nice if we could get them directly from the MR values and don't have to fake them from the total size. -- To view, visit https://review.coreboot.org/c/coreboot/+/68871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Gerrit-Change-Number: 68871 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 01:15:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mem_chip_info: Update to new format
by Julius Werner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Shelley Chen, Yu-Ping Wu. Hello Shelley Chen, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68871 to look at the new patch set (#2). Change subject: mem_chip_info: Update to new format ...................................................................... mem_chip_info: Update to new format The original version of the mem_chip_info structure does not record rank information and does not allow precise modeling of certain DDR configurations, so it falls short on its purpose to compile all available memory information. This patch updates the format to a new layout that remedies these issues. Since the structure was introduced so recently that no firmware using it has been finalized and shipped yet, we should be able to get away with this without accounting for backwards compatibility. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h M src/soc/mediatek/common/memory.c 2 files changed, 104 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68871/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Gerrit-Change-Number: 68871 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Add functions to store/restore uart state in smm
by 9elements QA (Code Review) 26 Oct '22

26 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68567 ) Change subject: soc/intel/xeon_sp: Add functions to store/restore uart state in smm ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130770 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130769 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130768 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130767 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130766 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130765 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130764 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130763 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130762 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130761 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130760 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130759 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130758 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130757 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130756 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130755 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484 Gerrit-Change-Number: 68567 Gerrit-PatchSet: 6 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 00:48:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mem_chip_info: Update to new format
by Julius Werner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Shelley Chen, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68871 ) Change subject: mem_chip_info: Update to new format ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Open comment to make sure this doesn't get merged before the corresponding QcLib update lands, but it's ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/68871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Gerrit-Change-Number: 68871 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 00:21:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mem_chip_info: Update to new format
by Julius Werner (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Shelley Chen, Yu-Ping Wu. Hello Shelley Chen, Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68871 to review the following change. Change subject: mem_chip_info: Update to new format ...................................................................... mem_chip_info: Update to new format The original version of the mem_chip_info structure does not record rank information and does not allow precise modeling of certain DDR configurations, so it falls short on its purpose to compile all available memory information. This patch updates the format to a new layout that remedies these issues. Since the structure was introduced so recently that no firmware using it has been finalized and shipped yet, we should be able to get away with this without accounting for backwards compatibility. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 1 file changed, 86 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68871/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h index 0d92b52..37d8e40 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h +++ b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h @@ -13,23 +13,81 @@ MEM_CHIP_LPDDR4X = 0x49, }; +/* This structure describes memory topology by channel, rank and DDR chip. + * + * Definitions: + * channel: A DDR channel is an entire set of DDR pins (including DQ, CS, CA, etc.) coming + * out of the DDR controller on the SoC. An SoC may support one or more DDR + * channels. The DDR chips on different channels are entirely independent from one + * another and not aware of each others' existence (concepts like dual-channel + * mode / channel-interleaving only exist inside the DDR controller and are not + * relevant to this topology description). + * chip: A physically distinct DDR part on the mainboard, with a single "channel" worth + * of pins (DQ, CS, CA, etc.). Parts that combine multiple "channels" worth of + * pins in one package (e.g. separate DQ[0]_A and DQ[0]_B) count as multiple + * separate chips in this description. + * rank: DDR ranks are independent sub-units within a single physical DDR chip. Each DDR + * transaction only communicates with one rank, which is selected through the CS + * pins. + * MRx: Mode registers, as defined in the various (LP)DDR specs. Mode registers are + * read through the DQ and written through the CA pins, and each rank on each chip + * has a separate mode register as selected by the CS pins. + * + * The basic purpose of this structure is to record information read from the mode registers on + * all ranks of all chips on all channels, to later allow the recipient of this information to + * reconstruct the topology and exact parts used on the board. Since each system may have a + * variable number of channels, and the chips on those channels may each have a variable number + * of ranks, this would require a doubly-nested structure with variable array sizes in both + * dimensions. The size and offset calculations in such a structure would become very cumbersome + * and error-prone, so instead this design just stores a one-dimensional array of "entries" + * where each entry stores information about one specific rank on one specific channel. This + * means that information which is specific to the channel itself is duplicated among all such + * entries for all ranks on that channel, and in a well-formed instance of this structure the + * values in per-channel fields (`type` and `channel_io_width`) among all entries that have the + * same value in the `channel` field MUST be identical. + * + * The information read from the mode registers should be decoded into normal integer values, + * but not otherwise adjusted in any way. For example, if the value read from MR8 on an LPDDR4 + * chip is 0b00010000, the `density_mbits` field should be set to 8192 (MR8[5:2] = 0b0100 + * decoded to 8192 Mbits) and the `io_width` field should be set to 16 (MR8[7:6] = 0b00 decoded + * to x16. + * + * Note that on some systems the I/O width (number of DQ pins) of the SoC controller's channel + * is a multiple of the I/O width on the DDR chip (which is the reason the two are recorded + * separately in this structure). This means that two identical DDR chips are wired in parallel + * on the same channel (e.g. one 16-bit part is wired to DQ[0:15] and the other to DQ[16:31]). + * All other pins beside DQ are shorted together in this configuration. This means that only the + * mode registers of the first chip can be read and recorded in this structure (and all mode + * register writes automatically write the same value to all chips through the shorted CA pins). + * The other chips are reported "implicitly" via the mismatch in I/O width. + * + * That means that the total amount of memory in bytes available on the whole system is: + * + * SUM[over all entries](density_mbits * (channel_io_width/io_width)) * 1024 * 1024 / 8 + */ struct mem_chip_info { - uint8_t type; /* enum mem_chip_type */ - uint8_t num_channels; - uint8_t reserved[6]; - struct mem_chip_channel { - uint64_t density; /* number in _bytes_, not Megabytes! */ - uint8_t io_width; /* should be `8`, `16`, `32` or `64` */ + uint8_t num_entries; + uint8_t reserved[3]; + struct mem_chip_entry { + uint8_t channel; /* Channel number this entry belongs to */ + uint8_t rank; /* Rank number within that channel */ + + /* per-channel information */ + uint8_t type; /* enum mem_chip_type */ + uint8_t channel_io_width; /* I/O width of the channel (no. of DQ pins on SoC) */ + + /* per-rank information */ + uint32_t density_mbits; /* density in megabits, decoded from MR8 */ + uint8_t io_width; /* I/O width of the DDR chip, decoded from MR8 */ uint8_t manufacturer_id; /* raw value from MR5 */ uint8_t revision_id[2]; /* raw values from MR6 and MR7 */ - uint8_t reserved[4]; uint8_t serial_id[8]; /* LPDDR5 only, MR47 - MR54 */ - } channel[0]; + } entries[0]; }; static inline size_t mem_chip_info_size(struct mem_chip_info *info) { - return sizeof(*info) + sizeof(info->channel[0]) * info->num_channels; + return sizeof(*info) + sizeof(info->entries[0]) * info->num_entries; }; #endif /* _COMMONLIB_BSD_MEM_CHIP_INFO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Gerrit-Change-Number: 68871 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS
by Eric Lai (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Haribalaraman Ramasubramanian, Reka Norman, Rizwan Qureshi, Tim Wawrzynczak, Daniil Lunev, Meera Ravindranath, Nick Vaccaro, Divagar Mohandass. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 ) Change subject: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Gerrit-Change-Number: 68251 Gerrit-PatchSet: 9 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Daniil Lunev <dlunev(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Daniil Lunev <dlunev(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 00:17:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/{adl, cmn}: Allow config to select the OCP workaround
by Eric Lai (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Subrata Banik, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Meera Ravindranath. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68309 ) Change subject: soc/intel/{adl, cmn}: Allow config to select the OCP workaround ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Gerrit-Change-Number: 68309 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 00:17:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory parts
by Tim Van Patten (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Nien, EricKY Cheng, Martin Roth. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68642 ) Change subject: mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory parts ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68642/comment/1e77bf39_5db347a4 PS2, Line 13: TEST=emerge-skyrim coreboot Have you booted a winterhold device with this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/68642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aa6169c6e824318e738878f8cd19e76fcfd5713 Gerrit-Change-Number: 68642 Gerrit-PatchSet: 2 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 23:54:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022