coreboot-gerrit October 2022

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[M] Change in coreboot[master]: drivers/ipmi/ocp: add functions to get board configuration
by Shuming Chu (Shuming) (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Paul Menzel, Jingle Hsu. Shuming Chu (Shuming) has uploaded a new patch set (#3) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/68779 ) Change subject: drivers/ipmi/ocp: add functions to get board configuration ...................................................................... drivers/ipmi/ocp: add functions to get board configuration These functions are added for ramstage: * add IPMI OEM command to get board configuration. * add function to get blade index in the sled. Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Change-Id: I85ec7ba68d580c13e368e7d656dba47ea043d33e --- M src/drivers/ipmi/ocp/Makefile.inc M src/drivers/ipmi/ocp/ipmi_ocp.h M src/drivers/ipmi/ocp/ipmi_sel.c 3 files changed, 59 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/68779/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ec7ba68d580c13e368e7d656dba47ea043d33e Gerrit-Change-Number: 68779 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: drivers/ipmi/ocp: add PCIe SEL support
by Shuming Chu (Shuming) (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Rocky Phagura, Paul Menzel. Shuming Chu (Shuming) has uploaded a new patch set (#3) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/68758 ) Change subject: drivers/ipmi/ocp: add PCIe SEL support ...................................................................... drivers/ipmi/ocp: add PCIe SEL support Add Kconfig SOC_RAS_BMS_SEL and corresponding support for generating PCIe error SEL records and sending them to BMC. Add PCIe error definitions. This is needed for SMM, so build the ipmi kcs driver in SMM. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65 --- M src/drivers/ipmi/Makefile.inc M src/drivers/ipmi/ocp/Kconfig M src/drivers/ipmi/ocp/Makefile.inc M src/drivers/ipmi/ocp/ipmi_ocp.h A src/drivers/ipmi/ocp/ipmi_sel.c 5 files changed, 248 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/68758/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65 Gerrit-Change-Number: 68758 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[master]: util/superiotool/fintek.c: adding support for Fintek F81966 Super I/O...
by Tobias Schmid (Code Review) 26 Oct '22

26 Oct '22

Tobias Schmid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68885 ) Change subject: util/superiotool/fintek.c: adding support for Fintek F81966 Super I/O chip ...................................................................... util/superiotool/fintek.c: adding support for Fintek F81966 Super I/O chip Signed-off-by: Tobias Schmid <tobiasschmidch(a)gmail.com> Change-Id: I372d94f26e86d2533be7d374970276aca4a5db0c --- M util/superiotool/fintek.c 1 file changed, 641 insertions(+), 589 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/68885/1 diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index 2dcb131..ce65f80 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -1,589 +1,631 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include "superiotool.h" - -#define DEVICE_ID_BYTE1_REG 0x20 -#define DEVICE_ID_BYTE2_REG 0x21 - -#define VENDOR_ID_BYTE1_REG 0x23 -#define VENDOR_ID_BYTE2_REG 0x24 - -#define FINTEK_VENDOR_ID 0x3419 - -static const struct superio_registers reg_table[] = { - {0x0106, "F71862FG / F71863FG", { /* Same ID? Datasheet typo? */ - /* We assume reserved bits are read as 0. */ - {NOLDN, NULL, - {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, - 0x2b,0x2c,0x2d,EOT}, - {0x06,0x01,0x19,0x34,0x00,0x00,MISC,0x00,0x00,0x00, - 0x00,0x00,0x08,EOT}}, - {0x0, "Floppy", - {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, - {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, - {0x1, "COM1", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x2, "COM2", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, - {0x3, "Parallel port", - {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, - {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, - {0x4, "Hardware monitor", - {0x30,0x60,0x61,0x70,EOT}, - {0x01,0x02,0x95,0x00,EOT}}, - {0x5, "Keyboard", - {0x30,0x60,0x61,0x70,0x72,EOT}, - {0x01,0x00,0x60,0x00,0x00,EOT}}, - {0x6, "GPIO", - {0xf0,0xf1,0xf2,0xf3,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1, - 0xd2,0xd3,0xc0,0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3, - EOT}, - {0x00,0x0f,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0xff, - NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0x3f,NANA,0x00, - EOT}}, - {0x7, "VID", - {0x30,0x60,0x61, 0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6, - 0xf7,EOT}, - {0x00,0x00,0x00, 0x00,0x00,MISC,0x00,NANA,0x00,0x00, - 0x00,EOT}}, - {0x8, "SPI", - {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa, - 0xfb,0xfc,0xfd,0xfe,0xff,EOT}, - {0x10,0x04,0x01,NANA,0x00,0x00,0x00,NANA,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,EOT}}, - {0xa, "PME, ACPI", - {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT}, - {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}}, - {EOT}}}, - {0x0110, "F71808A", { - /* We assume reserved bits are read as 0. */ - {NOLDN, NULL, - {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28, - 0x29,0x2a,0x2b,0x2c,0x2d,EOT}, - {0x00,0x00,0x10,0x01,0x19,0x34,0x00,0x00,MISC,0x00, - 0xc0,0x21,0x2f,0x5c,0x27,EOT}}, - {0x1, "COM1", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x4, "Hardware monitor", - {0x30,0x60,0x61,0x70,EOT}, - {0x01,0x02,0x95,0x00,EOT}}, - {0x5, "Keyboard", - {0x30,0x60,0x61,0x70,0x72,0xfe,0xff,EOT}, - {0x01,0x00,0x60,0x01,0x0c,0x01,0x29,EOT}}, - {0x6, "GPIO", - {0x70,0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xcb,0xcc, - 0xcd,0xce,0xcf,0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6, - 0xd7,0xd8,0xe0,0xe1,0xe2,0xe3,0xf0,0xf1,0xf2,0xf3, - EOT}, - {0x00,0x00,0x3f,NANA,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0xe0,0x40,0x00,0x00,NANA,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x1f,NANA,0x00,0x00,0xff,NANA,0x00, - EOT}}, - {0x7, "WDT", - {0x30,0x60,0x61,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, - EOT}, - {0x00,0x00,0x00,0x03,NANA,NANA,NANA,0x00,0x0a,0x00, - EOT}}, - {0x8, "CIR", - {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf8,0xf9,0xfa,0xfb, - 0xfc,0xfd,0xfe,EOT}, - {0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x80,0x3b, - 0x00,0x00,0x00,EOT}}, - {0xa, "PME, ACPI, and EUP Power Saving", - {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, - 0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, - 0xf6,0xf7,0xf8,0xf9,0xfa,0xfd,EOT}, - {0x00,0x10,0xcc,0x0c,0x13,0x09,0xc7,0x09,0x63,0x00, - 0x0f,0x00,0x00,0x00,0x00,NANA,0x00,NANA,0x06,0x3c, - 0x1f,0x00,0x00,0x00,0x00,NANA,EOT}}, - {EOT}}}, - {0x0710, "F71869A/AD", { - /* We assume reserved bits are read as 0. */ - {NOLDN, NULL, - {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28, - 0x29,0x29,0x2a,0x2a,0x2b,0x2b,0x2c,0x2c,0x2d,EOT}, - {0x00,0x00,0x10,0x07,0x19,0x34,0x00,0x00,NANA,0x38, - 0x6f,0x03,0x0f,0xe7,0x0f,NANA,0x00,NANA,0x28,EOT}}, - {0x0, "Floppy", - {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, - {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, - {0x1, "COM1", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x2, "COM2", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, - {0x3, "Parallel port", - {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, - {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, - {0x4, "Hardware monitor", - {0x30,0x60,0x61,0x70,EOT}, - {0x01,0x02,0x95,0x00,EOT}}, - {0x5, "Keyboard", - {0x30,0x60,0x61,0x70,0x72,0xf0,0xfe,0xff,EOT}, - {0x01,0x00,0x60,0x01,0x0c,0x83,0x81,0x29,EOT}}, - {0x6, "GPIO", - {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,0xe0,0xe1, - 0xe2,0xe3,0xe4,0xe5,0xe6,0xd0,0xd1,0xd2,0xd3,0xc0, - 0xc1,0xc2,0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xa0, - 0xa1,0xa2,0xa4,0xa5,0xa6,0xa9,0xab,0xac,0xad,0xae, - 0xaf,0x90,0x91,0x92,0x80,0x81,0x82,0x83,EOT}, - {0x00,0x00,0x00,0x00,0x00,0x3f,NANA,0x00,0x00,0xff, - NANA,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0x00, - 0xff,NANA,0x00,0x0f,NANA,0x00,0x00,0x00,0x00,0x00, - 0x1f,NANA,0x00,0x00,0x00,0x00,0x00,0xe0,0x00,0x00, - 0x40,0x00,0xff,NANA,0x00,0xff,NANA,0x00,EOT}}, - {0x7, "WDT", - {0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, - {0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}}, - {0x8, "CIR", - {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf8,0xf9,0xfa,0xfb, - 0xfc,0xfd,0xfe,EOT}, - {0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x80,0x3b, - 0x00,0x00,0x00,EOT}}, - {0xa, "PME, ACPI, and ERP Power Saving", - {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, - 0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, - 0xf6,0xf7,0xf8,0xf9,0xfa,0xfc,0xfe,EOT}, - {0x00,0x00,0xcc,0x3c,0x13,0x09,0xc7,0x09,0x63,0x08, - 0x0f,0x00,0x00,0x00,0x00,NANA,0x00,NANA,0x06,0x1c, - 0x1f,0x86,0x00,0x00,0x00,0x07,0x00,EOT}}, - {EOT}}}, - {0x1408, "F71869E/ED", { - /* We assume reserved bits are read as 0. */ - {NOLDN, NULL, - {0x02,0x07,0x20,0x21,0x23,0x24,0x26,0x27,0x28,0x29, - 0x2a,0x2b,0x2d,EOT}, - {0x00,0x00,0x08,0x14,0x19,0x34,0x00,NANA,0x38,0x6f, - 0x07,0x0f,0x28,EOT}}, - {0x00, "FDC", - {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, - {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, - {0x01, "UART1", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x02, "UART2", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, - {0x03, "Parallel port", - {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, - {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, - {0x04, "Hardware Monitor", - {0x30,0x60,0x61,0x70,EOT}, - {0x01,0x02,0x95,0x00,EOT}}, - {0x05, "KBC", - {0x30,0x60,0x61,0x70,0x72,0xf0,0xfe,0xff,EOT}, - {0x01,0x00,0x60,0x01,0x0c,0x83,0x81,0x29,EOT}}, - {0x06, "GPIO", - {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,0xe0,0xe1, - 0xe2,0xe3,0xe4,0xe5,0xe6,0xd0,0xd1,0xd2,0xd3,0xc0, - 0xc1,0xc2,0xb0,0xb1,0xb2,0xb3,0xa0,0xa1,0xa2,0xa3, - 0x90,0x91,0x92,0x93,EOT}, - {0x00,0x00,0x00,0x00,0x00,0x3f,NANA,0x00,0x00,0xff, - NANA,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0x00, - 0xff,NANA,0x00,0x0f,NANA,0x00,0x00,0x1f,NANA,0x00, - 0x00,0x3f,NANA,0x00,EOT}}, - {0x07, "WDT", - {0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, - {0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}}, - {0x0a, "PME, ACPI, and EUP Power Saving", - {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, - 0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, - 0xf8,0xf9,0xfe,EOT}, - {0x00,0x00,0xcc,0x3c,0x13,0x09,0xc7,0x09,0x63,0x08, - 0x00,0x00,0x00,0x00,0x00,NANA,0x06,0x1c,0x1f,0x86, - 0x00,0x00,0x00,EOT}}, - {EOT}}}, - {0x2307, "F71889", { - /* We assume reserved bits are read as 0. */ - {NOLDN, NULL, - {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b, - 0x2c,0x2d,EOT}, - {0x07,0x23,0x19,0x34,0x00,0x00,0x00,0x00,0xf0,0x30, - 0x00,0x08,EOT}}, - {0x0, "Floppy", - {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, - {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, - {0x1, "COM1", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x2, "COM2", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, - {0x3, "Parallel port", - {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, - {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, - {0x4, "Hardware monitor", - {0x30,0x60,0x61,0x70,EOT}, - {0x01,0x02,0x95,0x00,EOT}}, - {0x5, "Keyboard", - {0x30,0x60,0x61,0x70,0x72,0xfe,EOT}, - {0x01,0x00,0x60,0x01,0x0c,0x81,EOT}}, - {0x6, "GPIO", - {0x80,0x81,0x82,0x83,0x90,0x91,0x92,0x93,0xa0,0xa1, - 0xa2,0xa3,0xb0,0xb1,0xb2,0xc0,0xc1,0xc2,0xc3,0xd0, - 0xd1,0xd2,0xd3,0xe0,0xe1,0xe2,0xe3,0xf0,0xf1,0xf2, - 0xf3,0xfe,0xff,EOT}, - {0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0x1f, - NANA,0x00,0x00,0xff,NANA,0x00,0xff,NANA,0x00,0x00, - 0xff,NANA,0x00,0x00,0x7f,NANA,0x00,0x00,0x7f,NANA, - 0x00,0x00,0x00,EOT}}, - {0x7, "VID", - {0x30,0x60,0x61,EOT}, - {0x00,0x00,0x00,EOT}}, - {0x8, "SPI", - {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa, - 0xfb,0xfc,0xfd,0xfe,0xff,EOT}, - {0x00,RSVD,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,EOT}}, - {0xa, "PME, ACPI", - {0x30,0xf0,0xf1,0xf4,0xf5,0xf6,EOT}, - {0x00,0x00,0x00,0x26,0x1c,0x07,EOT}}, - {0xb, "VREF", - {0xf0,0xf1,0xf2,0xf3,0xff,EOT}, - {0x64,0x64,0x64,0x00,0x00,EOT}}, - {EOT}}}, - {0x4103, "F71872F/FG / F71806F/FG", { /* Same ID? Datasheet typo? */ - {NOLDN, NULL, - {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, - 0x29,0x2a,0x2b,0x2c,0x2d,EOT}, - {0x03,0x41,RSVD,0x19,0x34,0x00,0x00,MISC,0x66, - 0x80,0x00,0x00,0x00,0x04,EOT}}, - {0x0, "Floppy", - {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, - {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, - {0x1, "COM1", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x2, "COM2", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, - {0x3, "Parallel port", - {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, - {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, - {0x4, "Hardware monitor", - {0x30,0x60,0x61,0x70,EOT}, - {0x00,0x02,0x95,0x00,EOT}}, - {0x5, "Keyboard", /* Only documented on F71872F/FG. */ - {0x30,0x60,0x61,0x70,0x72,0xf0,0xf1,EOT}, - {0x01,0x00,0x60,0x00,0x00,0x83,0x00,EOT}}, - {0x6, "GPIO", - {0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, - 0xe9,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8, - EOT}, - {0x00,0x00,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00, - 0x7f,0x00,0x7f,NANA,0x00,0xff,NANA,0x00,0x03,NANA, - EOT}}, - {0x7, "VID", - {0x30,0x60,0x61,EOT}, - {0x00,0x00,0x00,EOT}}, - {0xa, "PME, ACPI", - {0x30,0xf0,0xf1,0xf4,0xf5,EOT}, - {0x00,0x00,0x61,0x06,0x3c,EOT}}, - {EOT}}}, - {0x4105, "F71882FG/F71883FG", { /* Same ID? Datasheet typo? */ - /* We assume reserved bits are read as 0. */ - {NOLDN, NULL, - {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, - 0x2b,0x2c,0x2d,EOT}, - {0x05,0x41,0x19,0x34,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x08,0x08,EOT}}, - {0x0, "Floppy", - {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, - {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, - {0x1, "COM1", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x2, "COM2", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, - {0x3, "Parallel port", - {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, - {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, - {0x4, "Hardware monitor", - {0x30,0x60,0x61,0x70,EOT}, - {0x01,0x02,0x95,0x00,EOT}}, - {0x5, "Keyboard", - {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, - {0x01,0x00,0x60,0x00,0x00,0x83,EOT}}, - {0x6, "GPIO", - {0x70,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1,0xd2,0xd3,0xc0, - 0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xf0,0xf1,0xf2, - 0xf3,EOT}, - {0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00, - 0x0f,NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0xff,NANA, - 0x00,EOT}}, - {0x7, "VID", - {0x30,0x60,0x61,EOT}, - {0x00,0x00,0x00,EOT}}, - {0x7, "SPI", - {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa, - 0xfb,0xfc,0xfd,0xfe,0xff,EOT}, - {0x10,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,EOT}}, - {0xa, "PME, ACPI", - {0x30,0xf0,0xf1,0xf4,0xf5,EOT}, - {0x00,0x00,0x01,0x06,0x1c,EOT}}, - {EOT}}}, - {0x0604, "F71805F/FG", { - /* We assume reserved bits are read as 0. */ - {NOLDN, NULL, - {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,EOT}, - {0x04,0x06,0x19,0x34,0x00,0x00,0x3f,0x08,0x00,EOT}}, - {0x0, "Floppy", - {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, - {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, - {0x1, "COM1", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x2, "COM2", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, - {0x3, "Parallel port", - {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, - {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, - {0x4, "Hardware monitor", - {0x30,0x60,0x61,0x70,EOT}, - {0x00,0x02,0x95,0x00,EOT}}, - {0x6, "GPIO", - {0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, - 0xe9,0xf0,0xf1,0xf3,0xf4,EOT}, - {0x00,0x00,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,NANA,0x00,NANA,EOT}}, - {0xa, "PME", - {0x30,0xf0,0xf1,EOT}, - {0x00,0x00,0x00,EOT}}, - {EOT}}}, - {0x0581, "F8000", { /* Fintek/ASUS F8000 */ - {EOT}}}, - {0x0802, "F81216D/DG", { - {NOLDN, NULL, - {0x25,0x2f,EOT}, - {0x00,RSVD,EOT}}, - {0x0, "UART1", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {NANA,NANA,NANA,NANA,0x00,0x40,EOT}}, - {0x1, "UART2", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {NANA,NANA,NANA,NANA,0x00,EOT}}, - {0x2, "UART3", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {NANA,NANA,NANA,NANA,0x00,EOT}}, - {0x3, "UART4", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {NANA,NANA,NANA,NANA,0x00,EOT}}, - {0x8, "WDT", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x00,NANA,NANA,NANA,NANA,NANA,EOT}}, - {EOT}}}, - {0x1602, "F81216AD", { - {NOLDN, NULL, - {0x25,0x27,EOT}, - {0x00,NANA,EOT}}, - {0x0, "UART1", - {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf4,0xf5,EOT}, - {NANA,NANA,NANA,NANA,0x00,0x40,0x00,0x00,EOT}}, - {0x1, "UART2", - {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT}, - {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}}, - {0x2, "UART3", - {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT}, - {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}}, - {0x3, "UART4", - {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT}, - {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}}, - {0x8, "WDT", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x00,NANA,NANA,NANA,NANA,NANA,EOT}}, - {EOT}}}, - {0x0407, "F81865F/F-I", { - {NOLDN, NULL, - {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2a,0x2b,0x2c,0x2d,EOT}, - {NANA,0x00,0x07,0x04,0x19,0x34,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x1f,0x00,0x08,EOT}}, - {0x00, "FDC", - {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, - {NANA,0x03,0xf0,NANA,NANA,NANA,NANA,NANA,EOT}}, - {0x03, "LPT", - {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, - {NANA,0x03,0x78,NANA,NANA,NANA,EOT}}, - {0x04, "HWMON", - {0x30,0x60,0x61,0x70,EOT}, - {NANA,0x02,0x95,NANA,EOT}}, - {0x05, "KBC", - {0x30,0x60,0x61,0x70,0x72,0xfe,0xf0,EOT}, - {NANA,0x00,0x60,NANA,NANA,NANA,0x71,EOT}}, - {0x06, "GPIO", - {0x30,0x60,0x61,0x70,0xf1,0xf2,0xf3,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xe0,0xe1,0xe2,0xe3,0xef,0xd0,0xd1,0xd2,0xd3,0xc0,0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xa0,0xa1,0xa2,0xa3,0x90,0x91,0x92,0x93,EOT}, - {NANA,0x00,0x60,NANA,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,NANA,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,NANA,NANA,NANA,NANA,EOT}}, - {0x07, "WDT", - {0x30,0x60,0x61,0xf5,0xf6,0xfa,EOT}, - {NANA,0x00,0x00,0x00,0x00,NANA,EOT}}, - {0x08, "SPI", - {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, - {0x10,0x04,NANA,NANA,0x00,0x00,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, - {0x0a, "PME & ACPI", - {0x30,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT}, - {NANA,NANA,NANA,NANA,NANA,0x06,NANA,0x00,EOT}}, - {0x0b, "RTC", - {0x30,0x60,0x61,0x70,EOT}, - {NANA,0x00,0x00,NANA,EOT}}, - {0x10, "UART1", - {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, - {NANA,0x03,0xf8,NANA,NANA,NANA,0x00,0x00,EOT}}, - {0x11, "UART2", - {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, - {NANA,0x02,0xf8,NANA,NANA,NANA,0x00,0x00,EOT}}, - {0x12, "UART3", - {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, - {NANA,0x03,0xe8,NANA,NANA,NANA,0x00,0x00,EOT}}, - {0x13, "UART4", - {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, - {NANA,0x02,0xe8,NANA,NANA,NANA,0x00,0x00,EOT}}, - {0x14, "UART5", - {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, - {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}}, - {0x15, "UART6", - {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, - {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}}, - {EOT}}}, - {0x1010, "F81866", { - {EOT}}}, - {0x0215, "F81962/F81964/F81966/F81967", { - {EOT}}}, - {EOT} -}; - -static const struct superio_registers hwm_table[] = { - {0x0110, "F71808A", { - {NOLDN, NULL, - {0x01, 0x02, 0x03, 0x08, 0x0a, 0x0b, 0x0c, 0x0d, - 0x0f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - /* 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, */ - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x66, 0x6b, 0x6c, - 0x6d, 0x6f, 0x7f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x98, - 0x9b, 0x9c, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xec, 0xed, 0xee, - 0xef, EOT}, - {0x03, 0x00, 0x01, 0x4c, 0x00, 0x00, 0x55, 0x00, - 0x20, - NANA, NANA, NANA, NANA, RSVD, RSVD, RSVD, NANA, - NANA, RSVD, RSVD, RSVD, RSVD, NANA, NANA, NANA, - /* RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, - RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, */ - 0x44, 0x00, NANA, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x40, - 0x04, 0x00, 0x00, - RSVD, RSVD, NANA, RSVD, NANA, RSVD, RSVD, RSVD, - NANA, NANA, NANA, NANA, NANA, RSVD, RSVD, - RSVD, RSVD, NANA, NANA, NANA, NANA, RSVD, RSVD, - RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, - 0x00, NANA, NANA, 0x00, 0x2e, 0xff, 0x05, 0x44, - 0x05, 0x55, 0x66, 0x00, - 0x03, 0xff, 0x00, 0x83, 0x03, 0xff, 0x3c, 0x32, - 0x28, 0x1e, 0xff, 0xd9, 0xb2, 0x99, 0x80, 0x1d, - 0x0c, 0x25, 0x00, 0x80, 0x03, 0xff, 0x3c, 0x32, - 0x28, 0x1e, 0xff, 0xd9, 0xb2, 0x99, 0x80, 0x1e, - 0x0f, 0xff, RSVD, 0x7f, RSVD, RSVD, RSVD, RSVD, - RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, 0x00, - NANA, NANA, NANA, NANA, NANA, 0x00, 0x01, 0x01, - 0x00, EOT}}, - {EOT}}}, - {EOT} -}; - -void probe_idregs_fintek(uint16_t port) -{ - uint16_t vid, did, hwmport; - - probing_for("Fintek", "", port); - - enter_conf_mode_winbond_fintek_ite_8787(port); - - did = regval(port, DEVICE_ID_BYTE1_REG); - did |= (regval(port, DEVICE_ID_BYTE2_REG) << 8); - - vid = regval(port, VENDOR_ID_BYTE1_REG); - vid |= (regval(port, VENDOR_ID_BYTE2_REG) << 8); - - if (vid != FINTEK_VENDOR_ID || superio_unknown(reg_table, did)) { - if (verbose) - printf(NOTFOUND "vid=0x%04x, id=0x%04x\n", vid, did); - exit_conf_mode_winbond_fintek_ite_8787(port); - return; - } - - printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", - get_superio_name(reg_table, did), vid, did, port); - chip_found = 1; - - dump_superio("Fintek", reg_table, port, did, LDN_SEL); - - if (extra_dump) { - regwrite(port, LDN_SEL, 0x04); /* Select LDN 4 (HWM). */ - - /* Get HWM base address (stored in LDN 4, index 0x60/0x61). */ - hwmport = regval(port, 0x60) << 8; - hwmport |= regval(port, 0x61); - - printf("Hardware monitor (0x%04x)\n", hwmport); - dump_superio("Fintek-HWM", hwm_table, hwmport, did, LDN_SEL); - } - - exit_conf_mode_winbond_fintek_ite_8787(port); -} - - -void probe_idregs_fintek_alternative(uint16_t port) -{ - uint16_t vid, did; - - probing_for("Fintek", "", port); - - enter_conf_mode_fintek_7777(port); - - did = regval(port, DEVICE_ID_BYTE1_REG); - did |= (regval(port, DEVICE_ID_BYTE2_REG) << 8); - - vid = regval(port, VENDOR_ID_BYTE1_REG); - vid |= (regval(port, VENDOR_ID_BYTE2_REG) << 8); - - if (vid != FINTEK_VENDOR_ID || superio_unknown(reg_table, did)) { - if (verbose) - printf(NOTFOUND "vid=0x%04x, id=0x%04x\n", vid, did); - exit_conf_mode_fintek_7777(port); - return; - } - - printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", - get_superio_name(reg_table, did), vid, did, port); - chip_found = 1; - - dump_superio("Fintek", reg_table, port, did, LDN_SEL); - - exit_conf_mode_fintek_7777(port); -} - -void print_fintek_chips(void) -{ - print_vendor_chips("Fintek", reg_table); -} +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "superiotool.h" + +#define DEVICE_ID_BYTE1_REG 0x20 +#define DEVICE_ID_BYTE2_REG 0x21 + +#define VENDOR_ID_BYTE1_REG 0x23 +#define VENDOR_ID_BYTE2_REG 0x24 + +#define FINTEK_VENDOR_ID 0x3419 + +static const struct superio_registers reg_table[] = { + {0x0106, "F71862FG / F71863FG", { /* Same ID? Datasheet typo? */ + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, + 0x2b,0x2c,0x2d,EOT}, + {0x06,0x01,0x19,0x34,0x00,0x00,MISC,0x00,0x00,0x00, + 0x00,0x00,0x08,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,EOT}, + {0x01,0x00,0x60,0x00,0x00,EOT}}, + {0x6, "GPIO", + {0xf0,0xf1,0xf2,0xf3,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1, + 0xd2,0xd3,0xc0,0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3, + EOT}, + {0x00,0x0f,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0xff, + NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0x3f,NANA,0x00, + EOT}}, + {0x7, "VID", + {0x30,0x60,0x61, 0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6, + 0xf7,EOT}, + {0x00,0x00,0x00, 0x00,0x00,MISC,0x00,NANA,0x00,0x00, + 0x00,EOT}}, + {0x8, "SPI", + {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa, + 0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0x10,0x04,0x01,NANA,0x00,0x00,0x00,NANA,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI", + {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT}, + {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}}, + {EOT}}}, + {0x0110, "F71808A", { + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,EOT}, + {0x00,0x00,0x10,0x01,0x19,0x34,0x00,0x00,MISC,0x00, + 0xc0,0x21,0x2f,0x5c,0x27,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xfe,0xff,EOT}, + {0x01,0x00,0x60,0x01,0x0c,0x01,0x29,EOT}}, + {0x6, "GPIO", + {0x70,0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xcb,0xcc, + 0xcd,0xce,0xcf,0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6, + 0xd7,0xd8,0xe0,0xe1,0xe2,0xe3,0xf0,0xf1,0xf2,0xf3, + EOT}, + {0x00,0x00,0x3f,NANA,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0xe0,0x40,0x00,0x00,NANA,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x1f,NANA,0x00,0x00,0xff,NANA,0x00, + EOT}}, + {0x7, "WDT", + {0x30,0x60,0x61,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, + EOT}, + {0x00,0x00,0x00,0x03,NANA,NANA,NANA,0x00,0x0a,0x00, + EOT}}, + {0x8, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe,EOT}, + {0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x80,0x3b, + 0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI, and EUP Power Saving", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, + 0xf6,0xf7,0xf8,0xf9,0xfa,0xfd,EOT}, + {0x00,0x10,0xcc,0x0c,0x13,0x09,0xc7,0x09,0x63,0x00, + 0x0f,0x00,0x00,0x00,0x00,NANA,0x00,NANA,0x06,0x3c, + 0x1f,0x00,0x00,0x00,0x00,NANA,EOT}}, + {EOT}}}, + {0x0710, "F71869A/AD", { + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x29,0x2a,0x2a,0x2b,0x2b,0x2c,0x2c,0x2d,EOT}, + {0x00,0x00,0x10,0x07,0x19,0x34,0x00,0x00,NANA,0x38, + 0x6f,0x03,0x0f,0xe7,0x0f,NANA,0x00,NANA,0x28,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,0xfe,0xff,EOT}, + {0x01,0x00,0x60,0x01,0x0c,0x83,0x81,0x29,EOT}}, + {0x6, "GPIO", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,0xe0,0xe1, + 0xe2,0xe3,0xe4,0xe5,0xe6,0xd0,0xd1,0xd2,0xd3,0xc0, + 0xc1,0xc2,0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xa0, + 0xa1,0xa2,0xa4,0xa5,0xa6,0xa9,0xab,0xac,0xad,0xae, + 0xaf,0x90,0x91,0x92,0x80,0x81,0x82,0x83,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x3f,NANA,0x00,0x00,0xff, + NANA,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0x00, + 0xff,NANA,0x00,0x0f,NANA,0x00,0x00,0x00,0x00,0x00, + 0x1f,NANA,0x00,0x00,0x00,0x00,0x00,0xe0,0x00,0x00, + 0x40,0x00,0xff,NANA,0x00,0xff,NANA,0x00,EOT}}, + {0x7, "WDT", + {0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}}, + {0x8, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe,EOT}, + {0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x80,0x3b, + 0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI, and ERP Power Saving", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, + 0xf6,0xf7,0xf8,0xf9,0xfa,0xfc,0xfe,EOT}, + {0x00,0x00,0xcc,0x3c,0x13,0x09,0xc7,0x09,0x63,0x08, + 0x0f,0x00,0x00,0x00,0x00,NANA,0x00,NANA,0x06,0x1c, + 0x1f,0x86,0x00,0x00,0x00,0x07,0x00,EOT}}, + {EOT}}}, + {0x1408, "F71869E/ED", { + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x23,0x24,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2d,EOT}, + {0x00,0x00,0x08,0x14,0x19,0x34,0x00,NANA,0x38,0x6f, + 0x07,0x0f,0x28,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x01, "UART1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x02, "UART2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x03, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x04, "Hardware Monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x05, "KBC", + {0x30,0x60,0x61,0x70,0x72,0xf0,0xfe,0xff,EOT}, + {0x01,0x00,0x60,0x01,0x0c,0x83,0x81,0x29,EOT}}, + {0x06, "GPIO", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,0xe0,0xe1, + 0xe2,0xe3,0xe4,0xe5,0xe6,0xd0,0xd1,0xd2,0xd3,0xc0, + 0xc1,0xc2,0xb0,0xb1,0xb2,0xb3,0xa0,0xa1,0xa2,0xa3, + 0x90,0x91,0x92,0x93,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x3f,NANA,0x00,0x00,0xff, + NANA,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0x00, + 0xff,NANA,0x00,0x0f,NANA,0x00,0x00,0x1f,NANA,0x00, + 0x00,0x3f,NANA,0x00,EOT}}, + {0x07, "WDT", + {0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}}, + {0x0a, "PME, ACPI, and EUP Power Saving", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,0xfe,EOT}, + {0x00,0x00,0xcc,0x3c,0x13,0x09,0xc7,0x09,0x63,0x08, + 0x00,0x00,0x00,0x00,0x00,NANA,0x06,0x1c,0x1f,0x86, + 0x00,0x00,0x00,EOT}}, + {EOT}}}, + {0x2307, "F71889", { + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b, + 0x2c,0x2d,EOT}, + {0x07,0x23,0x19,0x34,0x00,0x00,0x00,0x00,0xf0,0x30, + 0x00,0x08,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xfe,EOT}, + {0x01,0x00,0x60,0x01,0x0c,0x81,EOT}}, + {0x6, "GPIO", + {0x80,0x81,0x82,0x83,0x90,0x91,0x92,0x93,0xa0,0xa1, + 0xa2,0xa3,0xb0,0xb1,0xb2,0xc0,0xc1,0xc2,0xc3,0xd0, + 0xd1,0xd2,0xd3,0xe0,0xe1,0xe2,0xe3,0xf0,0xf1,0xf2, + 0xf3,0xfe,0xff,EOT}, + {0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0x1f, + NANA,0x00,0x00,0xff,NANA,0x00,0xff,NANA,0x00,0x00, + 0xff,NANA,0x00,0x00,0x7f,NANA,0x00,0x00,0x7f,NANA, + 0x00,0x00,0x00,EOT}}, + {0x7, "VID", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x8, "SPI", + {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa, + 0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0x00,RSVD,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI", + {0x30,0xf0,0xf1,0xf4,0xf5,0xf6,EOT}, + {0x00,0x00,0x00,0x26,0x1c,0x07,EOT}}, + {0xb, "VREF", + {0xf0,0xf1,0xf2,0xf3,0xff,EOT}, + {0x64,0x64,0x64,0x00,0x00,EOT}}, + {EOT}}}, + {0x4103, "F71872F/FG / F71806F/FG", { /* Same ID? Datasheet typo? */ + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,EOT}, + {0x03,0x41,RSVD,0x19,0x34,0x00,0x00,MISC,0x66, + 0x80,0x00,0x00,0x00,0x04,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", /* Only documented on F71872F/FG. */ + {0x30,0x60,0x61,0x70,0x72,0xf0,0xf1,EOT}, + {0x01,0x00,0x60,0x00,0x00,0x83,0x00,EOT}}, + {0x6, "GPIO", + {0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8, + EOT}, + {0x00,0x00,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00, + 0x7f,0x00,0x7f,NANA,0x00,0xff,NANA,0x00,0x03,NANA, + EOT}}, + {0x7, "VID", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI", + {0x30,0xf0,0xf1,0xf4,0xf5,EOT}, + {0x00,0x00,0x61,0x06,0x3c,EOT}}, + {EOT}}}, + {0x4105, "F71882FG/F71883FG", { /* Same ID? Datasheet typo? */ + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, + 0x2b,0x2c,0x2d,EOT}, + {0x05,0x41,0x19,0x34,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x08,0x08,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x00,0x83,EOT}}, + {0x6, "GPIO", + {0x70,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1,0xd2,0xd3,0xc0, + 0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xf0,0xf1,0xf2, + 0xf3,EOT}, + {0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00, + 0x0f,NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0xff,NANA, + 0x00,EOT}}, + {0x7, "VID", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x7, "SPI", + {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa, + 0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0x10,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI", + {0x30,0xf0,0xf1,0xf4,0xf5,EOT}, + {0x00,0x00,0x01,0x06,0x1c,EOT}}, + {EOT}}}, + {0x0604, "F71805F/FG", { + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,EOT}, + {0x04,0x06,0x19,0x34,0x00,0x00,0x3f,0x08,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x02,0x95,0x00,EOT}}, + {0x6, "GPIO", + {0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf1,0xf3,0xf4,EOT}, + {0x00,0x00,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,NANA,0x00,NANA,EOT}}, + {0xa, "PME", + {0x30,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,EOT}}, + {EOT}}}, + {0x0581, "F8000", { /* Fintek/ASUS F8000 */ + {EOT}}}, + {0x0802, "F81216D/DG", { + {NOLDN, NULL, + {0x25,0x2f,EOT}, + {0x00,RSVD,EOT}}, + {0x0, "UART1", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x40,EOT}}, + {0x1, "UART2", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {NANA,NANA,NANA,NANA,0x00,EOT}}, + {0x2, "UART3", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {NANA,NANA,NANA,NANA,0x00,EOT}}, + {0x3, "UART4", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {NANA,NANA,NANA,NANA,0x00,EOT}}, + {0x8, "WDT", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, + {0x1602, "F81216AD", { + {NOLDN, NULL, + {0x25,0x27,EOT}, + {0x00,NANA,EOT}}, + {0x0, "UART1", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf4,0xf5,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x40,0x00,0x00,EOT}}, + {0x1, "UART2", + {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}}, + {0x2, "UART3", + {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}}, + {0x3, "UART4", + {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}}, + {0x8, "WDT", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, + {0x0407, "F81865F/F-I", { + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2a,0x2b,0x2c,0x2d,EOT}, + {NANA,0x00,0x07,0x04,0x19,0x34,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x1f,0x00,0x08,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {NANA,0x03,0xf0,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x03, "LPT", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {NANA,0x03,0x78,NANA,NANA,NANA,EOT}}, + {0x04, "HWMON", + {0x30,0x60,0x61,0x70,EOT}, + {NANA,0x02,0x95,NANA,EOT}}, + {0x05, "KBC", + {0x30,0x60,0x61,0x70,0x72,0xfe,0xf0,EOT}, + {NANA,0x00,0x60,NANA,NANA,NANA,0x71,EOT}}, + {0x06, "GPIO", + {0x30,0x60,0x61,0x70,0xf1,0xf2,0xf3,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xe0,0xe1,0xe2,0xe3,0xef,0xd0,0xd1,0xd2,0xd3,0xc0,0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xa0,0xa1,0xa2,0xa3,0x90,0x91,0x92,0x93,EOT}, + {NANA,0x00,0x60,NANA,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,NANA,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,NANA,NANA,NANA,NANA,EOT}}, + {0x07, "WDT", + {0x30,0x60,0x61,0xf5,0xf6,0xfa,EOT}, + {NANA,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x08, "SPI", + {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0x10,0x04,NANA,NANA,0x00,0x00,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "PME & ACPI", + {0x30,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT}, + {NANA,NANA,NANA,NANA,NANA,0x06,NANA,0x00,EOT}}, + {0x0b, "RTC", + {0x30,0x60,0x61,0x70,EOT}, + {NANA,0x00,0x00,NANA,EOT}}, + {0x10, "UART1", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, + {NANA,0x03,0xf8,NANA,NANA,NANA,0x00,0x00,EOT}}, + {0x11, "UART2", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, + {NANA,0x02,0xf8,NANA,NANA,NANA,0x00,0x00,EOT}}, + {0x12, "UART3", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, + {NANA,0x03,0xe8,NANA,NANA,NANA,0x00,0x00,EOT}}, + {0x13, "UART4", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, + {NANA,0x02,0xe8,NANA,NANA,NANA,0x00,0x00,EOT}}, + {0x14, "UART5", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, + {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}}, + {0x15, "UART6", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, + {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}}, + {EOT}}}, + {0x1010, "F81866", { + {EOT}}}, + {0x0215, "F81962/F81964/F81966/F81967", { + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2a,0x2b,0x2c,0x2d,EOT}, + {NANA,0x00,0x07,0x04,0x19,0x34,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x1f,0x00,0x08,EOT}}, + {0x03, "LPT", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {NANA,0x03,0x78,NANA,NANA,NANA,EOT}}, + {0x04, "HWMON", + {0x30,0x60,0x61,0x70,EOT}, + {NANA,0x02,0x95,NANA,EOT}}, + {0x05, "KBC", + {0x30,0x60,0x61,0x70,0x72,0xfe,EOT}, + {NANA,0x00,0x60,NANA,NANA,NANA,EOT}}, + {0x06, "GPIO", + {0x30,0x60,0x61,0x70,0x71,0x72,0x73,0x7e,0x7f,EOT}, + {NANA,0x00,0x60,NANA,0x00,NANA,0x00,0x00,0x00,EOT}}, + {0x07, "WDT", + {0x30,0x60,0x61,0xf5,0xf6,0xfa,EOT}, + {NANA,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x0a, "PME & ACPI & ERP", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,0x06,NANA,0x00,NANA,NANA,EOT}}, + {0x0f, "SPI", + {0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x03,EOT}}, + {0x10, "UART1", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {0x01,0x03,0xf8,0x04,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x11, "UART2", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {0x01,0x03,0xf8,0x04,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x12, "UART3", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {0x01,0x03,0xf8,0x04,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x13, "UART4", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {0x01,0x03,0xf8,0x04,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x14, "UART5", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {0x01,0x03,0xf8,0x04,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x15, "UART6", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {0x01,0x03,0xf8,0x04,NANA,0x04,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {EOT}}}, + {EOT} +}; + +static const struct superio_registers hwm_table[] = { + {0x0110, "F71808A", { + {NOLDN, NULL, + {0x01, 0x02, 0x03, 0x08, 0x0a, 0x0b, 0x0c, 0x0d, + 0x0f, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, + /* 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, */ + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x66, 0x6b, 0x6c, + 0x6d, 0x6f, 0x7f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x98, + 0x9b, 0x9c, 0x9e, 0x9f, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xec, 0xed, 0xee, + 0xef, EOT}, + {0x03, 0x00, 0x01, 0x4c, 0x00, 0x00, 0x55, 0x00, + 0x20, + NANA, NANA, NANA, NANA, RSVD, RSVD, RSVD, NANA, + NANA, RSVD, RSVD, RSVD, RSVD, NANA, NANA, NANA, + /* RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, + RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, */ + 0x44, 0x00, NANA, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x40, + 0x04, 0x00, 0x00, + RSVD, RSVD, NANA, RSVD, NANA, RSVD, RSVD, RSVD, + NANA, NANA, NANA, NANA, NANA, RSVD, RSVD, + RSVD, RSVD, NANA, NANA, NANA, NANA, RSVD, RSVD, + RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, + 0x00, NANA, NANA, 0x00, 0x2e, 0xff, 0x05, 0x44, + 0x05, 0x55, 0x66, 0x00, + 0x03, 0xff, 0x00, 0x83, 0x03, 0xff, 0x3c, 0x32, + 0x28, 0x1e, 0xff, 0xd9, 0xb2, 0x99, 0x80, 0x1d, + 0x0c, 0x25, 0x00, 0x80, 0x03, 0xff, 0x3c, 0x32, + 0x28, 0x1e, 0xff, 0xd9, 0xb2, 0x99, 0x80, 0x1e, + 0x0f, 0xff, RSVD, 0x7f, RSVD, RSVD, RSVD, RSVD, + RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, 0x00, + NANA, NANA, NANA, NANA, NANA, 0x00, 0x01, 0x01, + 0x00, EOT}}, + {EOT}}}, + {EOT} +}; + +void probe_idregs_fintek(uint16_t port) +{ + uint16_t vid, did, hwmport; + + probing_for("Fintek", "", port); + + enter_conf_mode_winbond_fintek_ite_8787(port); + + did = regval(port, DEVICE_ID_BYTE1_REG); + did |= (regval(port, DEVICE_ID_BYTE2_REG) << 8); + + vid = regval(port, VENDOR_ID_BYTE1_REG); + vid |= (regval(port, VENDOR_ID_BYTE2_REG) << 8); + + if (vid != FINTEK_VENDOR_ID || superio_unknown(reg_table, did)) { + if (verbose) + printf(NOTFOUND "vid=0x%04x, id=0x%04x\n", vid, did); + exit_conf_mode_winbond_fintek_ite_8787(port); + return; + } + + printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", + get_superio_name(reg_table, did), vid, did, port); + chip_found = 1; + + dump_superio("Fintek", reg_table, port, did, LDN_SEL); + + if (extra_dump) { + regwrite(port, LDN_SEL, 0x04); /* Select LDN 4 (HWM). */ + + /* Get HWM base address (stored in LDN 4, index 0x60/0x61). */ + hwmport = regval(port, 0x60) << 8; + hwmport |= regval(port, 0x61); + + printf("Hardware monitor (0x%04x)\n", hwmport); + dump_superio("Fintek-HWM", hwm_table, hwmport, did, LDN_SEL); + } + + exit_conf_mode_winbond_fintek_ite_8787(port); +} + + +void probe_idregs_fintek_alternative(uint16_t port) +{ + uint16_t vid, did; + + probing_for("Fintek", "", port); + + enter_conf_mode_fintek_7777(port); + + did = regval(port, DEVICE_ID_BYTE1_REG); + did |= (regval(port, DEVICE_ID_BYTE2_REG) << 8); + + vid = regval(port, VENDOR_ID_BYTE1_REG); + vid |= (regval(port, VENDOR_ID_BYTE2_REG) << 8); + + if (vid != FINTEK_VENDOR_ID || superio_unknown(reg_table, did)) { + if (verbose) + printf(NOTFOUND "vid=0x%04x, id=0x%04x\n", vid, did); + exit_conf_mode_fintek_7777(port); + return; + } + + printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", + get_superio_name(reg_table, did), vid, did, port); + chip_found = 1; + + dump_superio("Fintek", reg_table, port, did, LDN_SEL); + + exit_conf_mode_fintek_7777(port); +} + +void print_fintek_chips(void) +{ + print_vendor_chips("Fintek", reg_table); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372d94f26e86d2533be7d374970276aca4a5db0c Gerrit-Change-Number: 68885 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Schmid <tobiasschmidch(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: stoneyridge: Set the SPI read speed as 66MHz
by Bao Zheng (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68884 to review the following change. Change subject: stoneyridge: Set the SPI read speed as 66MHz ...................................................................... stoneyridge: Set the SPI read speed as 66MHz The SPI read mode for Family 15h in EFS header has been affected by these two patches. It causes the ChromeBook booting unstable. The old settings are all FF, which means nothing. So we can not just change it back. We just change the speed to "Normal", which I assume has the same effect with old settings. Tested on Grunt. https://review.coreboot.org/c/coreboot/+/58555 https://review.coreboot.org/c/coreboot/+/58871 BUG=b:247025109 TEST=Grunt Change-Id: Ia6083cfa515abeb2e981ff0ef825970c9311466b Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/gardenia/Kconfig M src/mainboard/amd/pademelon/Kconfig M src/mainboard/google/kahlee/Kconfig 3 files changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68884/1 diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 2925fd6..eed4f07 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -35,7 +35,7 @@ if !EM100 config EFS_SPI_READ_MODE - default 4 # Dual IO (1-2-2) + default 0 # Normal config EFS_SPI_SPEED default 0 # 66MHz diff --git a/src/mainboard/amd/pademelon/Kconfig b/src/mainboard/amd/pademelon/Kconfig index 9890d7f..593135f 100644 --- a/src/mainboard/amd/pademelon/Kconfig +++ b/src/mainboard/amd/pademelon/Kconfig @@ -65,7 +65,7 @@ if !EM100 config EFS_SPI_READ_MODE - default 4 # Dual IO (1-2-2) + default 0 # Normal config EFS_SPI_SPEED default 0 # 66MHz diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 8c8486e..cdd6d54 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -129,7 +129,7 @@ if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE - default 4 # Dual IO (1-2-2) + default 0 # Normal config EFS_SPI_SPEED default 0 # 66MHz -- To view, visit https://review.coreboot.org/c/coreboot/+/68884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6083cfa515abeb2e981ff0ef825970c9311466b Gerrit-Change-Number: 68884 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/common: Clean up includes
by 9elements QA (Code Review) 26 Oct '22

26 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68702 ) Change subject: soc/intel/common: Clean up includes ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130839 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130838 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130837 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130836 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130835 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130834 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130833 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130832 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130831 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130830 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130829 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130828 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130827 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130826 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130825 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130824 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Gerrit-Change-Number: 68702 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 06:42:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "soc/intel/systemagent.c: Fix memory type reporting"
by Werner Zeh (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68879 ) Change subject: Revert "soc/intel/systemagent.c: Fix memory type reporting" ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: I have the error introduced in CB:68405 100% reproducible on mc_ehl2 and sporadic on mc_ehl1. This revert fixes it for me. -- To view, visit https://review.coreboot.org/c/coreboot/+/68879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72da99c019241b627ce8b543937364a53a5fe97b Gerrit-Change-Number: 68879 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 26 Oct 2022 06:38:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "soc/intel/systemagent.c: Fix memory type reporting"
by Arthur Heymans (Code Review) 26 Oct '22

26 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68879 ) Change subject: Revert "soc/intel/systemagent.c: Fix memory type reporting" ...................................................................... Revert "soc/intel/systemagent.c: Fix memory type reporting" This reverts commit 9c2f3cc9d9b3b3b7cfe1e62a70ea3061ca6c15ac. This broke the smihandler for no clear reason on some platforms. Change-Id: I72da99c019241b627ce8b543937364a53a5fe97b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 19 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/68879/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 1938765..69e4197 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -201,8 +201,11 @@ sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> TOLUD */ - reserved_ram_from_to(dev, index++, top_of_ram, sa_map_values[SA_TOLUD_REG]); + /* + * top_of_ram -> TOLUD: This contains TSEG which needs to be uncacheable + * for proper operation of the smihandler. + */ + mmio_from_to(dev, index++, top_of_ram, sa_map_values[SA_TOLUD_REG]); /* 4GiB -> TOUUD */ upper_ram_end(dev, index++, sa_map_values[SA_TOUUD_REG]); -- To view, visit https://review.coreboot.org/c/coreboot/+/68879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72da99c019241b627ce8b543937364a53a5fe97b Gerrit-Change-Number: 68879 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/brya: Create marasov variant
by Frank Chu (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Paul Menzel, Nick Vaccaro. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68575 ) Change subject: mb/google/brya: Create marasov variant ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68575/comment/2e2c8676_d66c8b76 PS3, Line 2: FrankChu > Frank Chu […] My coreboot Username is FrankChu, no permission to change to add a space, this issue bother me long time on many CL, when git push coreboot CL, I need fill username/password mantually or sometimes I can't git push coreboot sucess or ger change-ID fail $ git push origin HEAD:refs/for/master Username for 'https://review.coreboot.org': FrankChu Password for 'https://FrankChu@review.coreboot.org': Is this serious rule about no space in name? Do you suggest, should I apply for another coreboot account? I will abandon this CL and submit other one to change Author Name https://review.coreboot.org/c/coreboot/+/68575/comment/e3c8ccb9_f44d6c02 PS3, Line 12: (Auto-Generated by create_coreboot_variant.sh version 4.5.0). > Please move the . inside, and fix the script. these content auto generate by ./src/platform/dev/contrib/variantcreate_coreboot_variant.sh -- To view, visit https://review.coreboot.org/c/coreboot/+/68575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2e30c203ee0dfa6c887a707e9b5074ce89f57ac Gerrit-Change-Number: 68575 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 06:07:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/google/chromec: Expand EC share memory for DTTS
by EricKY Cheng (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, Isaac Lee, Paul Menzel, Jon Murphy, Tim Wawrzynczak, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68077 ) Change subject: ec/google/chromec: Expand EC share memory for DTTS ...................................................................... Patch Set 18: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68077/comment/41abdcfe_694e45af PS15, Line 7: mb/google/skyrim/var/winterhold: DTT Switching Proposal > Please make this a statement by adding a verb (in imperative mood) [1]. […] Change to "Expand EC share memory for DTTS" https://review.coreboot.org/c/coreboot/+/68077/comment/c76be3c6_fe20dc4b PS15, Line 8: > Please describe the problem, that needs solving. Done https://review.coreboot.org/c/coreboot/+/68077/comment/134c2233_2c52a0a8 PS15, Line 9: Define mode change STTB bit for Desktop(1) and laptop(0) : This bit is Switch thermal table by body detection status > Please add a dot/period at the end of sentences, and add a space before the (. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Gerrit-Change-Number: 68077 Gerrit-PatchSet: 18 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Oct 2022 05:22:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/google/chromec: Expand EC share memory for DTTS
by EricKY Cheng (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Tim Wawrzynczak, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Isaac Lee, Jon Murphy, Tim Wawrzynczak, Martin Roth, Tim Van Patten, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68077 to look at the new patch set (#18). Change subject: ec/google/chromec: Expand EC share memory for DTTS ...................................................................... ec/google/chromec: Expand EC share memory for DTTS DTTS is Dynamic Thermal Table Switching Proposal. DTTS needs one bit to save the body detection result from EC. Define mode change STTB bit for Desktop (1) and laptop (0). This bit is Switch thermal table by body detection status. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/68077/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/68077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Gerrit-Change-Number: 68077 Gerrit-PatchSet: 18 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2022